Abstract: A column selection circuit is disclosed, in which a layout area is minimized by reducing the number of data bus lines and sensing speed characteristic is improved by reducing sensing time of a bit line.

Abstract: A semiconductor memory device is provided that enhances data output speed. The semiconductor uses dual memory arrays with differing activation voltage levels. The semiconductor memory includes a first memory cell array having multiple memory cells and a second memory cell array having more memory cells than the first memory cell array. First and second row decoders respectively receive first and second row addresses to respectively generate an activation signal for a word line in the first memory cell array and subsequent word lines in the second memory cell array. A column decoder receives and decodes a column address to generate a bit line selection signal for the first and second memory cell arrays. The semiconductor device further includes a sense amplifier, which is coupled to bit lines selected based on the bit line selection signals, that detects a potential difference between the bit lines caused by data and amplifies the potential difference.

Abstract: A charge pump circuit of a semiconductor memory device provides high efficiency. A high voltage detector outputs a high voltage detection signal. A regulator outputs a high level and a controller is triggered at a descent edge of a row access strobe bar signal and outputs a high level row access strobe bar pulse signal. An oscillator generates an oscillation pulse signal in accordance with the high level turn-on signal outputted from the regulator. A charge pump performs a pumping operation until the oscillation pulse signal reaches a potential of (Vdd+2Vt) when the oscillation pulse signal is applied thereto, and halts the pumping operation when the high level high voltage detection signal is applied. A pull-up transistor precharges the raised voltage Vpp to a potential of (Vdd-Vt) when power is turned on.

Abstract: An improved DRAM having a self-test function capable of performing a self-test function in a fast page mode in accordance with a transition of a column address in accordance with an interior clock signal without a toggle of a column address strobe signal, which includes an entry/exit control unit for generating a self-test entry signal in accordance with a combination a predetermined address signal and an external synchronous signal; a signal transition detection unit for detecting a transition of a self-test entry signal and a word line enable signal and for outputting a transition detection signal; a counter for counting an interior clock signal outputted in accordance with a transition detection signal; a data generating and comparison unit for writing and reading a test data without a toggle of the external synchronous signal comparing the read test data with the generated test data; and an error and end detection unit for generating an error flag and end flag.

Abstract: A back bias voltage generator comprising a power-on signal generator for generating a power-on signal when an external voltage remains at a constant level, a reference voltage generator for generating a reference voltage in response to the power-on signal from the power-on signal generator, an internal voltage generator for generating an internal voltage and an internal/external voltage select signal in response to the reference voltage from the reference voltage generator, the internal voltage being constant in level, a back bias voltage sensor for generating an oscillation enable signal in response to the external voltage or the internal voltage from the internal voltage generator under control of the internal/external voltage select signal from the internal voltage generator, an oscillator for generating an oscillating signal at a desired period and an enable signal in response to the oscillation enable signal from the back bias voltage sensor and outputting the generated enable signal to the internal volt

Abstract: A voltage generator for use in a semiconductor memory device suitable for use as a backbias voltage generator, as an internal high voltage generator, or as an internal power voltage generator. The present invention includes: a rectifier for producing a dc voltage power by rectifying clock signals; an oscillator including an odd number of invertors connected in series, and with the output of the last invertor fed back to the first invertor so as to oscillate clock pulses; and one or more bypass circuit connected so as for the output of the first invertor to bypass one or more intermediate invertors, and connected and disconnected by a control switch.