Abstract: A display substrate and a display device are provided. The display substrate includes a shift register unit, a first clock signal line and a first power line, the shift register unit includes a charge pump circuit, and the charge pump circuit includes a first capacitor, a first transistor and a second capacitor. The charge pump circuit is electrically connected with a first input node and a first node, respectively. A first electrode plate of the first capacitor is connected with the first clock signal line, a second electrode plate of the first capacitor is connected with the first input node, a first electrode plate of the second capacitor is connected with the first power line, a second electrode plate of the second capacitor is connected with the first node, a gate electrode of the first transistor is connected with a first electrode or a second electrode of the first transistor.

Abstract: An integrated circuit (IC) device includes memory cells each including first through fourth memory elements. The first memory element is physically arranged, along a first axis, between a bit line and a first auxiliary conductive line. The second memory element is physically arranged, along the first axis, between a second auxiliary conductive line and a first conductor. The first and second memory elements are arranged in a first row along the first axis. The third memory element is physically arranged, along the first axis, between the first auxiliary conductive line and a second conductor electrically coupled to the first conductor. The fourth memory element is physically arranged, along the first axis, between the bit line and the second auxiliary conductive line. The third and fourth memory elements are arranged, along the first axis, in a second row spaced from the first row along an axis transverse to the first axis.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: A method for evaluating energy efficiency of electric arc furnace steelmaking comprises: obtaining original smelting information of the electric arc furnace; processing the original smelting information, and calculating an electrical energy efficiency evaluation index and a chemical energy efficiency evaluation index for process operation; wherein the electrical energy efficiency evaluation index comprises circuit efficiency, transformer tap capacity utilization rate and electrical energy thermal efficiency, and the chemical energy efficiency evaluation index comprises oxygen utilization rate, carbon powder utilization rate and chemical energy thermal efficiency; and evaluating an energy utilization condition of the electric arc furnace comprehensively based on the electrical energy efficiency evaluation index and the chemical energy efficiency evaluation index.

Abstract: A vehicle electronic device is provided, including a vehicle window assembly, a first signal element, and a first protective element. The vehicle window assembly comprises a first protective substrate, a second protective substrate, and a display panel. The display panel is disposed between the first protective substrate and the second protective substrate. The first signal element is electrically connected to the display panel. The first protective element covers at least one portion of the first signal element.

Abstract: A magnetic tunnel junction (MTJ) memory cell and a metallic etch mask portion are formed over a substrate. At least one dielectric etch stop layer is deposited over the metallic etch mask portion, and a via-level dielectric layer is deposited over the at least one dielectric etch stop layer. A via cavity may be etched through the via-level dielectric layer, and a top surface of the at least one dielectric etch stop layer is physically exposed. The via cavity may be vertically extended by removing portions of the at least one dielectric etch stop layer and the metallic etch mask portion. A contact via structure is formed directly on a top surface of the top electrode in the via cavity to provide a low-resistance contact to the top electrode.

Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.

Abstract: The present application provides tricyclic urea compounds that modulate the activity of the V617F variant of JAK2, which are useful in the treatment of various diseases, including cancer.

Abstract: Aggregated log index-based log record identification is provided by maintaining log files of a database system on a plurality log storage devices, the log files including log records of changes to database objects, indexing the log files to obtain a collection of log indexes, where the indexing includes, for each log storage device, indexing log records stored on the log storage device to obtain a respective log index, then based on a request, identifying log storage devices that store log records for servicing the request, the log storage devices storing log indexes, of the collection of log indexes, that index an aggregate set of log records on the log storage devices, obtaining the log indexes from the log storage devices, and aggregating the log indexes to provide an aggregated log index that provides an index of the aggregate set of log records on the log storage devices.

Abstract: Embodiments of the present disclosure provide an array substrate and related display panel and display device. An array substrate, comprises: a substrate; a plurality of sub-pixels arranged in multiple rows and multiple columns provided on the substrate, at least one of the plurality of sub-pixels comprising pixel circuits, each of the pixel circuits comprising a driving circuit, a voltage stabilizing circuit, and a driving reset circuit, wherein the driving circuit is configured to provide a driving current to a light-emitting device, the voltage stabilizing circuit comprises a first voltage stabilizing circuit and a second voltage stabilizing circuit, the first voltage stabilizing circuit is configured to conduct a control terminal of the driving circuit with the driving reset circuit, the second voltage stabilizing circuit is configured to stabilize a voltage at the control terminal of the driving circuit, and the driving reset circuit is configured to reset the control terminal of the driving circuit.

Abstract: A composition and use thereof. The composition comprises an active component a and an active component b; the active component a is a compound as shown in general formula A; and the active component b is at least one of compounds which have insecticidal, acaricidal or bactericidal activity and are different from the compound as shown in general formula A. The composition has the advantages of synergistic effect and expanding prevention and treatment spectrum, and can be used for preventing and treating various pests, particularly mite damage, and plant diseases caused by various fungi, bacteria, nematodes and viruses.

Abstract: The present disclosure provides a tray assembly having a dual-structure. The tray assembly comprises an upper tray and a lower tray. The lower tray is capable of being easily disengaged from the upper tray by use of a dovetail joint that allows the lower tray to slidably move relative to the upper tray. The tray assembly also utilizes magnets to reduce the use of mechanical joints. The combination of the magnets together with the dovetail joint provides a quick and efficient way of sliding the lower tray in and out from the upper tray. The lower tray having a collection region collects any external, foreign materials generated during a chemical mechanical polishing/planarizing process. After the cleaning process, the lower tray can be slid back into the upper tray for use.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: A method is provided that includes: obtaining a first state information of the remote driving system, where the remote driving system is configured to perform remote control on a vehicle communicatively connected with the remote driving system; determining whether an abnormality occurs in the remote driving system based on the first state information; determining abnormality information of the remote driving system in response to the occurrence of the abnormality in the remote driving system; and adjusting a state of the remote control based on the abnormality information.

Abstract: An operating method of an optical system in a vehicle is provided. The optical system includes a display device. The display device includes a display panel and a plurality of light emitting units. The light emitting units are configured to emit a light to the display panel. The operating method includes the following steps. An emphasized portion of an object is determined. An image corresponding to the emphasized portion is displayed by the display device by adjusting a light intensity of at least a portion of the light emitted from the light emitting units.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

Abstract: An electric vehicle is provided, including: a main body, traveling wheels, a drive assembly and a controller. The traveling wheels are arranged on the main body. The drive assembly is arranged on the main body and includes a hub motor. The hub motor is arranged on the traveling wheels. The controller is used to control the hub motor.

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.