Patents by Inventor Yu Feng

Yu Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966352
    Abstract: An information handling system with modular riser components for receiving expansion cards having various requirements. The system includes a riser body assembly having a common support structure for receiving expansion cards. The common support structure may be coupled to different expansion structures to provide support of expansion cards having requirements that would not be met by the common support structure alone.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: April 23, 2024
    Assignee: Dell Products L.P.
    Inventors: Yu-Feng Lin, Hao-Cheng Ku, Yi-Wei Lu
  • Publication number: 20240126446
    Abstract: Described herein are systems, methods, and software to manage multi-type storage in a cluster computing environment. In one example, a host can identify health and performance information at a first time for each local data store on the host and a hyperconverged data store available to the host. The host can further identify health and performance information associated with the data stores at a second time and can compare the health and performance information at the first time and the second time to identify differences in the information. The host then communicates the differences to a second host in the computing environment.
    Type: Application
    Filed: December 6, 2022
    Publication date: April 18, 2024
    Inventors: Yang Yang, Yu Wu, Jin Feng, Hui Xu, Zhuocheng Shen, Rajesh Venkatasubramanian
  • Patent number: 11961546
    Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
  • Patent number: 11963407
    Abstract: Provided is an organic light-emitting diode display substrate, including: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein the source/drain layer includes at least one pair of first signal lines; the anode layer includes a common power line, wherein the common power line is provided with vent holes; overlapping areas between two first signal lines in each pair of the first signal lines and a projection pattern of the vent hole are equal, the overlapping area being greater than 0, wherein the projection pattern of the vent hole is a pattern of an orthographic projection of the vent hole in the common power line on the source/drain layer. A display panel and a display device are also provided.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: April 16, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Jiangnan Lu, Guangliang Shang, Can Zheng, Yu Feng, Libin Liu, Jie Zhang, Mei Li
  • Patent number: 11961444
    Abstract: The disclosure provides a transparent display device including a display panel. The display panel includes a display area, a non-display area, and a plurality of pixels. The non-display area is adjacent to the display area. The plurality of pixels are disposed in the display area. A difference between a transmittance of the display area and a transmittance of the non-display area is less than 30% of the transmittance of the display area.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: April 16, 2024
    Assignee: Innolux Corporation
    Inventors: Yu-Chia Huang, Yuan-Lin Wu, Tsung-Han Tsai, Kuan-Feng Lee
  • Publication number: 20240120306
    Abstract: A semiconductor package includes a die stack including a first semiconductor die having a first interconnect structure, and a second semiconductor die having a second interconnect structure direct bonding to the first interconnect structure of the first semiconductor die. The second interconnect structure includes connecting pads disposed in a peripheral region around the first semiconductor die. First connecting elements are disposed on the connecting pads, respectively. A substrate includes second connecting elements on a mounting surface of the substrate. The first connecting elements are electrically connected to the second connecting elements through an anisotropic conductive structure.
    Type: Application
    Filed: November 4, 2022
    Publication date: April 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Kuang Ho, Yu-Jie Lin, Yi-Feng Hsu
  • Publication number: 20240120316
    Abstract: The present disclosure relates to a semiconductor package, a semiconductor bonding structure and a method of fabricating the same. The semiconductor package includes a first chip, a second chip and a conductive structure, wherein the conductive structure is disposed at a side of the second chip and over a second upper surface of the first interconnection structure to electrically connect to the first interconnection structure. The semiconductor bonding structure includes a first substrate, a plurality of first interconnection structures, a plurality of chips and a plurality of conductive structures, wherein the conductive structures are respectively disposed at a side of each of the chips and over a second upper surface of each first interconnection structure, to electrically connect to each first interconnection.
    Type: Application
    Filed: November 17, 2022
    Publication date: April 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Kuang Ho, Yu-Jie Lin, Yi-Feng Hsu
  • Patent number: 11950780
    Abstract: A surgical instrument and a battery pack for use with the surgical instrument are disclosed. The surgical instrument includes a handle assembly, having a protruding portion; and a battery pack, detachably assembled on the handle assembly, operated by the protruding portion, and having a battery unit, where the battery pack includes a discharging system comprising a discharge element, and a switching member, operated to electrically connect the discharge element to the battery unit of the battery pack to form a discharge circuit, and having an initial open state, in which the discharge circuit is non-conductive, an intermediate open state, in which the switching member cooperates with the protruding portion to make the discharge circuit non-conductive, and a closed state, in which the switching member is separated from the protruding portion to make the discharge circuit conducting.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: April 9, 2024
    Assignee: REACH SURGICAL, INC.
    Inventors: Yu Li, Kai Wang, Rongxuan Feng
  • Patent number: 11954259
    Abstract: Glasses with gesture recognition function include a glasses frame and a gesture recognition system. The gesture recognition system is disposed on the glasses frame and configured to detect hand gestures in front of the glasses thereby generating a control command. The gesture recognition system transmits the control command to an electronic device to correspondingly control the electronic device.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: April 9, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Horng-Goung Lai, En-Feng Hsu, Meng-Huan Hsieh, Yu-Hao Huang, Nien-Tse Chen
  • Publication number: 20240113221
    Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The FinFET device structure also includes a metal silicide layer over the S/D structure, and the metal silicide layer is in contact with the isolation structure.
    Type: Application
    Filed: November 28, 2023
    Publication date: April 4, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsiung TSAI, Shahaji B. MORE, Cheng-Yi PENG, Yu-Ming LIN, Kuo-Feng YU, Ziwei FANG
  • Publication number: 20240110976
    Abstract: An electronic device and a method for performing clock gating in the electronic device are provided. The electronic device includes at least one function circuit, a device under test (DUT) circuit and at least one gating circuit. The function circuit is configured to operate according to at least one primary clock, and the DUT circuit is configured to operate according to at least one secondary clock. In addition, the clock gating circuit is configured to control whether to enable the primary clock according to at least one primary enable signal, and control whether to enable the secondary clock according to the primary enable signal and a secondary enable signal.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 4, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Ching-Feng Huang, Yu-Cheng Lo
  • Patent number: 11950427
    Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chih-Yu Chang
  • Patent number: 11947395
    Abstract: A foldable display device is provided by the present disclosure. The foldable display device includes a foldable display panel and a foldable cover. The foldable cover is adhered to the foldable display panel. The foldable cover includes an inner substrate, an outer substrate and a first adhesive. The first adhesive is disposed between the inner substrate and the outer substrate. A thickness of the first adhesive is ranged from 1 micrometer to 40 micrometers, and a ratio of the sum of the thickness of the first adhesive and a thickness of the inner substrate to a thickness of the foldable cover is greater than or equal to 0.5 and less than 1. In addition, the foldable display device further includes a second adhesive disposed between the foldable display panel and the foldable cover.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: April 2, 2024
    Assignee: InnoLux Corporation
    Inventors: Yuan-Lin Wu, Yu-Chia Huang, Kuan-Feng Lee
  • Patent number: 11944264
    Abstract: The present invention relates to the technical field of endoscopes, and discloses a confocal endoscope with a fixing device.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: April 2, 2024
    Assignee: HAINAN UNIVERSITY
    Inventors: Qian Liu, Ling Fu, Xiaoxiao Ma, Gang Zheng, Yu Feng
  • Patent number: 11947212
    Abstract: An electronic device which is capable of being bent in a first direction and includes a plurality of light-emitting units and a plurality of conductive patterns overlapping with at least a portion of the plurality of light-emitting units and extending in a second direction. The first direction and the second direction have an angle ? of not greater than 30 degrees.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: April 2, 2024
    Assignee: InnoLux Corporation
    Inventors: Yuan-Lin Wu, Yu-Chia Huang, Yu-Ting Huang, Kuan-Feng Lee, Chia-Hung Hsieh
  • Publication number: 20240107691
    Abstract: A display device includes first and second display modules and first and second turning pieces that include a first coupling piece, a first turning piece, a second turning piece, and a third turning piece, a second coupling piece and a guiding device. When the first and second display modules are switched between folding and unfolding, the first turning piece pivots relative to the first coupling piece and the second turning piece, and the third turning piece pivots relative to the second coupling piece and the second turning piece. When the display module is switched from folded to unfolded, the other side of the first display module relative to the side is pulled, the side of the first display module is guided by one end of the guiding device and slides to the other end, the first and second display modules are symmetrically unfolded with the side edge as the center.
    Type: Application
    Filed: December 8, 2023
    Publication date: March 28, 2024
    Inventors: CHIEN-FENG CHANG, TSUNG-HUAI LEE, YU-HUNG HSIAO, CHAN-PENG LIN, SHANG-CHIEN WU
  • Publication number: 20240105119
    Abstract: A pixel circuit, a driving method therefor and a display apparatus are provided. The pixel circuit includes a driving sub-circuit, a write sub-circuit, a compensation sub-circuit, a reset sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a leak-proof sub-circuit, a storage sub-circuit and a light-emitting element. The reset sub-circuit is configured to reset a fourth node under control of a signal of a light-emitting control signal terminal and reset a fifth node under control of a signal of a reset control signal terminal. The compensation sub-circuit is configured to compensate a threshold voltage of the driving sub-circuit to the fifth node under the control of a signal of a first scanning signal terminal. The leak-proof sub-circuit is configured to write a signal of the fifth node into a first node under control of a signal of a second scanning signal terminal.
    Type: Application
    Filed: April 23, 2021
    Publication date: March 28, 2024
    Inventors: Libin LIU, Li WANG, Guangliang SHANG, Yu FENG, Long HAN, Baoyun WU, Shiming SHI
  • Patent number: 11943933
    Abstract: A memory device includes metal interconnect structures embedded within dielectric material layers that overlie a top surface of a substrate, a thin film transistor embedded in a first dielectric material layer selected from the dielectric material layers, and is vertically spaced from the top surface of the substrate, and a ferroelectric memory cell embedded within the dielectric material layers. A first node of the ferroelectric memory cell is electrically connected to a node of the thin film transistor through a subset of the metal interconnect structures that is located above, and vertically spaced from, the top surface of the substrate.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Bo-Feng Young, Mauricio Manfrini, Sai-Hooi Yeong, Han-Jong Chia, Yu-Ming Lin
  • Patent number: 11942358
    Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 11942007
    Abstract: A transparent display device is provided. The transparent display device includes a display unit having a circuit area and a transparent area. The display unit includes a plurality of signal lines located in the circuit area, a plurality of pixel circuits electrically connected to the signal lines and located in the circuit area, a plurality of light-emitting elements driven by the pixel circuits and located in the circuit area, and an encapsulation layer located in the circuit area and the transparent area. A first thickness of the encapsulation layer located in the circuit area is different from a second thickness of the encapsulation layer located in the transparent area.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: March 26, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Yu-Chia Huang, Tsung-Han Tsai, Kuan-Feng Lee