Patents by Inventor Yu Feng

Yu Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240094141
    Abstract: The present disclosure provides a method for processing defect information of a product, which includes the following steps of: acquiring defect information on a current film layer and defect information on historical film layers; determining whether defect information exists at a target location of the historical film layer if defect information exists at a target location of the current film layer; if defect information exists for a corresponding location to the target location in at least one of the historical film layers, deleting the defect information detected at the target location in the current film layer; and if no defect information exists for the target location in any of the historical film layers, retaining the defect information detected at the target location in the current film layer.
    Type: Application
    Filed: April 30, 2021
    Publication date: March 21, 2024
    Inventors: Haijin WANG, Chuan WANG, Tian LAN, Jianmin WU, Yu FENG, Hong WANG, Yu WANG, Fan ZHANG, Jiawei REN, Jing XUE, Jianfeng ZENG
  • Publication number: 20240099149
    Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Feng Yin, Min-Kun Dai, Chien-Hua Huang, Chung-Te Lin
  • Publication number: 20240096297
    Abstract: In some examples, a controller of a wearable device causes display by the wearable device of a test image, and adjusts a color property of the displayed test image. In response to an input provided by a user responsive to the displayed test image as the color property is adjusted, the controller determines a distribution of color wavelengths for an eye of the user, and detects a color vision deficiency of the user based on the determined distribution of color wavelengths. The controller provides control information to control a display device of the wearable device to compensate for the color vision deficiency.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Inventors: Hsiang-Ta Ke, Yu-Ren Chen, Chun-Feng Li
  • Publication number: 20240097067
    Abstract: A manufacturing method of an electronic element module is provided. The method includes: disposing a plurality of first micro-light-emitting diodes on a first temporary substrate; and replacing at least one defective micro-light-emitting diode of the first micro-light-emitting diodes with at least one second micro-light-emitting diode. The first micro-light-emitting diodes and at least one second micro-light-emitting diode are distributed on the first temporary substrate. The first micro-light-emitting diodes and at least one second micro-light-emitting diode have same properties, and at least one of the appearance difference, the height difference and the orientation difference exists between the first micro-light-emitting diodes and at least one second micro-light-emitting diode. A semiconductor structure and a display panel are also provided.
    Type: Application
    Filed: December 4, 2023
    Publication date: March 21, 2024
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Bo-Wei Wu, Yu-Yun Lo, Chien-Chen Kuo, Chang-Feng Tsai, Tzu-Yang Lin
  • Publication number: 20240097038
    Abstract: A semiconductor device, including a substrate, a first source/drain region, a second source/drain region, and a gate structure, is provided. The substrate has an extra body portion and a fin protruding from a top surface of the substrate, wherein the fin spans the extra body portion. The first source/drain region and the second source/drain region are in the fin. The gate structure spans the fin, is located above the extra body portion, and is located between the first source/drain region and the second source/drain region.
    Type: Application
    Filed: October 13, 2022
    Publication date: March 21, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Yi Chuen Eng, Tzu-Feng Chang, Teng-Chuan Hu, Yi-Wen Chen, Yu-Hsiang Lin
  • Patent number: 11935920
    Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
  • Patent number: 11935439
    Abstract: A stretchable electronic device includes a first electronic unit including a first light emitting element, a second electronic unit including a second light emitting element and disposed adjacent to the first electronic unit, and an elasticity layer having a connecting region connecting the first display unit and the second display unit. In a top view of the stretchable electronic device, a size difference between the connecting region before stretching and the connecting region after stretching is greater than a size difference between the first electronic unit before stretching and the first electronic unit after stretching.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: March 19, 2024
    Assignee: InnoLux Corporation
    Inventors: Yu-Chia Huang, Yuan-Lin Wu, Kuan-Feng Lee
  • Patent number: 11935793
    Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240085647
    Abstract: An optical fiber combiner includes optical fiber components including a predetermined area and a refractive index portion formed on the predetermined area; a housing including a channel with the optical fiber components disposed through, fastening members for fastening the optical fiber components, and a cover for sealing the channel; and a conductive material disposed in the channel. In response to laser beams impinging on the optical fiber components, heat is generated by the refractive index portion, the heat is absorbed by the conductive material, and the heat is further transferred to the housing and the cover by thermal conduction for dissipation.
    Type: Application
    Filed: October 17, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Hsiang Lin, Chin-Feng Su
  • Publication number: 20240090231
    Abstract: An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Yi-Ching Liu, Sai-Hooi Yeong, Yih Wang, Yu-Ming Lin
  • Publication number: 20240087514
    Abstract: A pixel circuit and a driving method therefor, an array substrate and a display device are provided. The pixel circuit includes a driving circuit, a data writing circuit, a first initialization circuit. The driving circuit is configured to control a driving current; the data writing circuit is configured to write a data signal into the control terminal of the driving circuit; the first initialization circuit is configured to apply a first initialization voltage to the control terminal of the driving circuit, and includes a first transistor; the data writing circuit includes a second transistor and the driving circuit includes a third transistor; semiconductor materials of active layers of both the first transistor and the second transistor have a smaller leakage current characteristic than a semiconductor material of a third active layer of the third transistor.
    Type: Application
    Filed: July 11, 2022
    Publication date: March 14, 2024
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Yu Feng, Libin Liu, Tian Dong
  • Publication number: 20240087960
    Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Lien HUANG, Ching-Feng FU, Huan-Just LIN, Fu-Sheng LI, Tsai-Jung HO, Bor Chiuan HSIEH, Guan-Xuan CHEN, Guan-Ren WANG
  • Publication number: 20240090236
    Abstract: A magnetic tunnel junction memory device includes a vertical stack of magnetic tunnel junction NOR strings located over a substrate. Each magnetic tunnel junction NOR string includes a respective semiconductor material layer that contains a semiconductor source region, a plurality of semiconductor channels, and a plurality of semiconductor drain regions, a plurality of magnetic tunnel junction memory cells having a respective first electrode that is located on a respective one of the plurality of semiconductor drain regions, and a metallic bit line contacting each second electrode of the plurality of magnetic tunnel junction memory cells. The vertical stack of magnetic tunnel junction NOR strings may be repeated along a channel direction to provide a three-dimensional magnetic tunnel junction memory device.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Han-Jong CHIA, Bo-Feng YOUNG, Sai-Hooi YEONG, Chenchen Jacob WANG, Meng-Han LIN, Yu-Ming LIN
  • Patent number: 11929634
    Abstract: Provided by the present application are a Direct Current (DC) micro-grid system, a charging loop circuit and a control method thereof. The charging loop circuit selectively connects a charging loop to a first side loop or a second side loop through a set of switches.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: March 12, 2024
    Assignee: Gree Electric Appliances, Inc. of Zhuhai
    Inventors: Shiyong Jiang, Xiang Zhang, Chongyang Feng, Ningning Chen, Meng Li, Yu Zhang
  • Patent number: 11928261
    Abstract: The disclosure provides a display device. The display device includes a display panel and a vibration generating module. The vibration generating module is attached to the display panel and includes a substrate, a circuit layer, and a plurality of vibrators. The circuit layer and the plurality of vibrators are disposed on the substrate, and the plurality of vibrators are electrically connected to the circuit layer.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: March 12, 2024
    Assignee: Innolux Corporation
    Inventors: Yu-Chia Huang, Yuan-Lin Wu, Hsiao-Lang Lin, Tsung-Han Tsai, Kuan-Feng Lee
  • Patent number: 11925457
    Abstract: A device for encouraging and guiding a spirometer user includes a housing, a main valve, a visual assembly, and a sound making assembly. The housing has a guiding channel, a first outlet channel, a second outlet channel, and an inlet channel. The main valve is disposed in a housing communicating with the guiding channel, the first outlet channel, the second outlet channel or the inlet channel and configured to regulate or control fluid flowing paths. The visual assembly includes a check valve in the second outlet channel, and at least one movable member. The sound making assembly includes a check valve and a sound maker. So, it can generate the visual and sound encouraging effects for learning how to use a spirometer correctly.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: March 12, 2024
    Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, CENTRAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Ming-Feng Wu, Yu-Hsuan Chen, Kuo-Chih Su, Chun-Hsiang Wang
  • Publication number: 20240080984
    Abstract: A package structure, including a circuit board, multiple circuit structure layers, at least one bridge structure, and at least one supporting structure, is provided. The circuit structure layer is disposed on the circuit board. The bridge structure is connected between the two adjacent circuit structure layers. The supporting structure is located between the two adjacent circuit structure layers, and the supporting structure has a first end and a second end opposite to each other and respectively connecting the bridge structure and the circuit board.
    Type: Application
    Filed: January 3, 2023
    Publication date: March 7, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Wei Huang, Ching-Feng Yu, Chih-Cheng Hsiao
  • Publication number: 20240081077
    Abstract: A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., National Yang Ming Chiao Tung University
    Inventors: Po-Tsun Liu, Meng-Han Lin, Zhen-Hao Li, Tsung-Che Chiang, Bo-Feng Young, Hsin-Yi Huang, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 11922855
    Abstract: An information handling system includes a host processing system and a Liquid Crystal Display device. The host processing system includes a graphics processing unit (GPU) and the LCD device includes a memory device and a DisplayPort Configuration Data (DPCD) register. The host processing system 1) determines whether the first GPU supports a Dynamic Display Shifting (DDS) mode, 2) when the GPU does not support the DDS mode, provides a first indication to the LCD device that the GPU does not support the DDS mode, and 3) when the GPU supports the DDS mode, provides a second indication to the LCD device that the GPU supports the DDS mode. The LCD device retrieves a Panel Self Refresh (PSR) setting from the memory device and stores the PSR setting to the DPCD register in response to the first indication, and retrieves a DDS setting from the memory and stores the DDS setting to the DPCD register in response to the second indication.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: March 5, 2024
    Assignee: Dell Products L.P.
    Inventors: Chun-Yi Chang, Yi-Fan Wang, Meng-Feng Hung, No-Hua Chuang, Yu Sheng Chang
  • Patent number: 11924534
    Abstract: This disclosure provides a lens assembly that has an optical path and includes a lens element and a light-blocking membrane layer. The lens element has an optical portion, and the optical path passes through the optical portion. The light-blocking membrane layer is coated on the lens element and adjacent to the optical portion. The light-blocking membrane layer has a distal side and a proximal side that is located closer to the optical portion than the distal side. The proximal side includes two extension structures and a recessed structure. Each of the extension structures extends along a direction away from the distal side, and the extension structures are not overlapped with each other in a direction in parallel with the optical path. The recessed structure is connected to the extension structures and recessed along a direction towards the distal side.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: March 5, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Jyun-Jia Cheng, Yu Chen Lai, Ming-Ta Chou, Cheng-Feng Lin, Chen-Yi Huang