Patents by Inventor Yu-Ling Lin

Yu-Ling Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10297723
    Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad on the semiconductor stack; a second pad on the semiconductor stack, wherein the first pad and the second pad are separated from each other with a distance, which define a region between the first pad and the second pad on the semiconductor stack; and multiple vias penetrating the active layer to expose the first semiconductor layer, wherein the first pad and the second pad are formed on regions other than the multiple vias.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: May 21, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Bo-Jiun Hu, Tsung-Hsun Chiang, Wen-Hung Chuang, Kuan-Yi Lee, Yu-Ling Lin, Chien-Fu Shen, Tsun-Kai Ko
  • Patent number: 10276295
    Abstract: A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Huan-Neng Chen, Yu-Ling Lin, Chin-Wei Kuo, Mei-Show Chen, Ho-Hsiang Chen, Min-Chie Jeng
  • Patent number: 10269746
    Abstract: Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Wei Kuo, Hsiao-Tsung Yen, Min-Chie Jeng, Yu-Ling Lin
  • Publication number: 20190111040
    Abstract: In accordance with the present invention, the immunoregulatory activity of low doses of P4N was investigated. Unlike previously described antitumor drugs, low dose P4N, in doses of about 1 to 10 mg/kg, or at concentrations of about 10 to 100 nM, was surprisingly found to contribute to humoral immunity by raising the titers and activities of autoantibodies against GRP78 and F1F0 ATP synthase on the surface of CT26 cells, and inducing B cell proliferation and differentiation of plasma cells. Methods for inducing endogenous antitumor autoantibodies (EAA) in a subject having a neoplasia comprising administering to the subject an effective amount of the nordihydroguaiaretic acid (NDGA) derivative P4N, or salts, solvates and stereoisomers thereof, as well as methods for inducing B cell proliferation, inducing BAFF stimulated B cell proliferation, and suppressing or inhibition growth of a neoplasia are also provided.
    Type: Application
    Filed: March 30, 2017
    Publication date: April 18, 2019
    Inventors: Ru Chih C. Huang, David Mold, Tiffany Jackson, Yu-Ling Lin, Kuang-Wen Liao
  • Patent number: 10199544
    Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad on the semiconductor stack; a second pad on the semiconductor stack, wherein the first pad and the second pad are separated from each other with a distance, which define a region between the first pad and the second pad on the semiconductor stack; and multiple vias penetrating the active layer to expose the first semiconductor layer, wherein the first pad and the second pad are formed on regions other than the multiple vias.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 5, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Bo-Jiun Hu, Tsung-Hsun Chiang, Wen-Hung Chuang, Kuan-Yi Lee, Yu-Ling Lin, Chien-Fu Shen, Tsun-Kai Ko
  • Patent number: 10192833
    Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: January 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Wei Kuo, Hui Yu Lee, Huan-Neng Chen, Yen-Jen Chen, Yu-Ling Lin, Chewn-Pu Jou
  • Publication number: 20190016028
    Abstract: The present subject matter relates to fabrication of micro-arc oxidation (MAO) based insert-molded components. In an example implementation, a method of fabricating a MAO based insert-molded component comprises forming an insert-molded component and oxidizing the insert-molded component through MAO. The insert-molded component has a metal body molded with a plastic body. On oxidation of the insert-molded component through MAO an oxide layer is formed on the metal body.
    Type: Application
    Filed: April 4, 2016
    Publication date: January 17, 2019
    Inventors: CHI HAO CHANG, KUAN-TING WU, YU-LING LIN
  • Publication number: 20180233471
    Abstract: An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.
    Type: Application
    Filed: April 6, 2018
    Publication date: August 16, 2018
    Inventors: Hsiao-Tsung Yen, Jhe-Ching Lu, Yu-Ling Lin, Chin-Wei Kuo, Min-Chie Jeng
  • Publication number: 20180233631
    Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad on the semiconductor stack; a second pad on the semiconductor stack, wherein the first pad and the second pad are separated from each other with a distance, which define a region between the first pad and the second pad on the semiconductor stack; and multiple vias penetrating the active layer to expose the first semiconductor layer, wherein the first pad and the second pad are formed on regions other than the multiple vias.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 16, 2018
    Inventors: Chao-Hsing CHEN, Jia-Kuen WANG, Tzu-Yao TSENG, Bo-Jiun HU, Tsung-Hsun CHIANG, Wen-Hung CHUANG, Kuan-Yi LEE, Yu-Ling LIN, Chien-Fu SHEN, Tsun-Kai KO
  • Publication number: 20180204958
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.
    Type: Application
    Filed: March 15, 2018
    Publication date: July 19, 2018
    Inventors: HSIAO-TSUNG YEN, YU-LING LIN, CHIN-WEI KUO, HO-HSIANG CHEN, CHEWN-PU JOU, MIN-CHIE JENG
  • Publication number: 20180145228
    Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad on the semiconductor stack; a second pad on the semiconductor stack, wherein the first pad and the second pad are separated from each other with a distance, which define a region between the first pad and the second pad on the semiconductor stack; and multiple vias penetrating the active layer to expose the first semiconductor layer, wherein the first pad and the second pad are formed on regions other than the multiple vias.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 24, 2018
    Inventors: Chao-Hsing CHEN, Jia-Kuen WANG, Tzu-Yao TSENG, Bo-Jiun HU, Tsung-Hsun CHIANG, Wen-Hung CHUANG, Kuan-Yi LEE, Yu-Ling LIN, Chien-Fu SHEN, Tsun-Kai KO
  • Patent number: 9960133
    Abstract: An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Jhe-Ching Lu, Yu-Ling Lin, Chin-Wei Kuo, Min-Chie Jeng
  • Patent number: 9923101
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Chewn-Pu Jou, Min-Chie Jeng
  • Patent number: 9893241
    Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad on the semiconductor stack; a second pad on the semiconductor stack, wherein the first pad and the second pad are separated from each other with a distance, which define a region between the first pad and the second pad on the semiconductor stack; and multiple vias penetrating the active layer to expose the first semiconductor layer, wherein the first pad and the second pad are formed on regions other than the multiple vias.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: February 13, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Bo-Jiun Hu, Tsung-Hsun Chiang, Wen-Hung Chuang, Kuan-Yi Lee, Yu-Ling Lin, Chien-Fu Shen, Tsun-Kai Ko
  • Publication number: 20170342137
    Abstract: The present invention relates to a monoclonal antibody that inhibits immunosuppressive functions of pathogens, antigen-binding fragment thereof, and hybridomas producing such antibody. The monoclonal antibody or antigen-binding fragment thereof bind to a peptide consisting an amino acid sequence represented by MEKVGKDGVITVE (SEQ ID NO: 1). The present invention also discloses use of the invented monoclonal antibody or antigen-binding fragment thereof, and method of preparation for such hybridomas.
    Type: Application
    Filed: May 26, 2016
    Publication date: November 30, 2017
    Inventors: Kuang-Wen Liao, Yu-Ling Lin, Ting-Yan Jian
  • Patent number: 9831173
    Abstract: A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ling Lin, Hsiao-Tsung Yen, Ho-Hsiang Chen, Chin-Wei Kuo, Chewn-Pu Jou
  • Patent number: 9728847
    Abstract: An antenna includes a plurality of upper electrodes in a first metal layer, a plurality of lower electrodes in a second metal layer, a plurality of side electrodes connecting the upper electrodes with the lower electrodes, and a ground structure. The upper electrodes, the lower electrodes and the side electrodes form one continuous electrode. The continuous electrode extends in a first direction away from a reference plane over a substrate. The upper electrodes extend in a second direction different from the first direction. The upper electrodes, the lower electrodes, and the side electrodes are embedded within a waveguide structure that includes a dielectric material. The substrate has a length extending in the first direction greater than a length the continuous electrode extends in the first direction. The waveguide structure includes a portion of the substrate in a region beyond the length of the continuous electrode in the first direction.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Hung, Yu-Ling Lin, Ho-Hsiang Chen
  • Publication number: 20170207253
    Abstract: The present invention provides an array substrate and a manufacturing method thereof. Etching stop patterns or auxiliary conductive patterns of a patterned auxiliary conductive layer are disposed corresponding to heavily doped regions of a patterned semiconductor layer, and source/drain electrodes may be electrically connected to the heavily doped regions via the etching stop patterns or the auxiliary conductive patterns. The production yield and the uniformity of electrical properties may be enhanced accordingly.
    Type: Application
    Filed: December 9, 2016
    Publication date: July 20, 2017
    Inventors: Chan-Jui LIU, Yu-Ling LIN, Chien-Hsun SHAN, Jia-Hua LIN
  • Patent number: 9658275
    Abstract: An apparatus includes three components. The first component includes a first transmission line; the second component is coupled with the first component and includes a second transmission line; and the third component electrically coupled with the first component and/or the second component. The transmission lines each include a substrate with a p-well or n-well within the substrate and a shielding layer over the p-well or n-well. The transmission lines also each include a plurality of intermediate conducting layers over the shielding layer, the plurality of intermediate conducting layers coupled by a plurality of vias. The transmission lines further each include a top conducting layer over the plurality of intermediate conducting layers.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Ho-Hsiang Chen, Sa-Lly Liu, Yu-Ling Lin
  • Publication number: 20170141260
    Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad on the semiconductor stack; a second pad on the semiconductor stack, wherein the first pad and the second pad are separated from each other with a distance, which define a region between the first pad and the second pad on the semiconductor stack; and multiple vias penetrating the active layer to expose the first semiconductor layer, wherein the first pad and the second pad are formed on regions other than the multiple vias.
    Type: Application
    Filed: November 14, 2016
    Publication date: May 18, 2017
    Inventors: Chao-Hsing CHEN, Jia-Kuen WANG, Tzu-Yao TSENG, Bo-Jiun HU, Tsung-Hsun CHIANG, Wen-Hung CHUANG, Kuan-Yi LEE, Yu-Ling LIN, Chien-Fu SHEN, Tsun-Kai KO