Patents by Inventor Yu Zhu

Yu Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11242075
    Abstract: Provided are a connection structure and system of an integrated brake device for a rail vehicle. The connection structure of an integrated brake device for a rail vehicle includes a brake valve, a dust collector, an intermediate body, an air cylinder, a support assembly and a connection assembly. The intermediate body is of a plate-type structure, the brake valve and the dust collector are mounted on one side of the intermediate body, the air cylinder is connected to the intermediate body by means of the connection assembly, the air cylinder is mounted on the other side of the intermediate body, and the support assembly is located between the air cylinder and the intermediate body. The connection structure of an integrated brake device for a rail vehicle has a simple and compact structure and saves on space.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: February 8, 2022
    Assignee: MEISHAN CRRC BRAKE SCIENCE & TECHNOLOGY CO., LTD.
    Inventors: Bali Xiao, Keming Li, Chao Lv, Yanfei Shen, Lei Xie, Hong An, Weiyuan Xiao, Chen Xiao, Yi Liu, Jianping Yang, Jianhong Shen, Yu Tian, Kaien Wang, Yu Zhu, Baohua Liu, Wenjun Liu, Bo Ning, Hai Xu, Dongfang Ou, Moukui Li
  • Publication number: 20220025972
    Abstract: The present disclosure relates to a sealing technology, and in particular relates to a high-vacuum or ultrahigh-vacuum seal gasket (301) for a flat plate structure and a sealing structure. The seal gasket (301) comprises a seal ring (302) and multiple metal wires (303) extending outwards from the seal ring (302). The flat plate sealing structure comprises two flat plates (401, 404), the seal gasket (301) is fixed to one flat plate (401) via the multiple extending metal wires (303) so as to accurately position the seal ring (302). Accurate positioning can be achieved by virtue of an extern force without structure improvement on flat plate workpieces, thereby ensuring that no malposition occurs after the installation of the seal gasket (301).
    Type: Application
    Filed: October 22, 2019
    Publication date: January 27, 2022
    Inventors: Rong CHENG, Yu ZHU, Kaiming YANG, Xiangbo LIU
  • Publication number: 20220021468
    Abstract: Apparatus and methods for envelope alignment calibration in radio frequency (RF) systems are provided. In certain embodiments, calibration is performed by providing an envelope signal that is substantially triangular along an envelope path, and by providing an RF signal to a power amplifier along an RF signal path. Additionally, an output of the power amplifier is observed to generate an observation signal using an observation receiver. The observation signal includes a first peak and a second peak, and a delay between the envelope signal and the RF signal is controlled based on relative size of the peaks of the observation signal to one another.
    Type: Application
    Filed: September 30, 2021
    Publication date: January 20, 2022
    Inventors: Florinel G. Balteanu, Yu Zhu, Paul T. DiCarlo
  • Publication number: 20220004769
    Abstract: Provided are a method and a device for constructing autonomous driving test scenes, a terminal and a readable storage media. Primitive scenes are extracted from real traffic scenes to establish a primitive scene description model. The values of the description variables are selected from distribution intervals of the description variables of the primitive scenes, and the description variables are randomly sampled based on the distribution of the description variables to generate test primitive scenes by adopting an importance sampling based Monte Carlo method. The test primitive scenes are recombined according to the parameters of the elements of the test scene to generate the test scene. The present invention can directly simulate the actual complex system, so as to avoid the result distortion caused by the simplification of the complex system.
    Type: Application
    Filed: December 26, 2020
    Publication date: January 6, 2022
    Inventors: Xiangmo ZHAO, Runmin WANG, Yu ZHU, Wenshuai ZHOU, Zhigang XU, Zhanwen LIU, Jingjun CHENG, Lan YANG, Pengpeng SUN
  • Publication number: 20210399122
    Abstract: The present application provides a semiconductor structure and a method for manufacturing the same, which solves a problem that an existing semiconductor structure is difficult to deplete a carrier concentration of a channel under a gate to realize an enhancement mode device. The semiconductor structure includes: a channel layer and a barrier layer superimposed in sequence, wherein a gate region is defined on a surface of the barrier layer; a plurality of trenches formed in the gate region, wherein the plurality of trenches extend into the channel layer; and a P-type semiconductor material filling the plurality of trenches.
    Type: Application
    Filed: September 2, 2021
    Publication date: December 23, 2021
    Inventors: Kai CHENG, Yu ZHU
  • Patent number: 11201620
    Abstract: A power supply circuit and an apparatus includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor, and a second capacitor. In this power supply circuit, one terminal of the first capacitor is connected to one terminal of the second capacitor, the other terminal of the first capacitor is separately connected to a first electrode of the first switching transistor and a first electrode of the second switching transistor, a second electrode of the first switching transistor is connected to a second electrode of the third switching transistor, a second electrode of the second switching transistor is connected to a second electrode of the fourth switching transistor, a third electrode of the first switching transistor is connected to an output node, and a third electrode of the second switching transistor is grounded.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: December 14, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Guorui Wang, Zheng Li, Chen Wang, Yu Zhu, Zhenming Zhang
  • Publication number: 20210384341
    Abstract: Disclosed are a semiconductor structure and a manufacturing method therefor, solving the problem that it is difficult for an existing semiconductor structure to deplete a carrier concentration of a channel under a gate so as to achieve an enhancement-mode device. The semiconductor structure comprises: a channel layer and a barrier layer stacked in sequence. A gate region is defined on a surface of the barrier layer; a plurality of trenches formed in the gate region. The plurality of trenches are extended into the channel layer; and a stress applying material filled in the plurality of trenches. A lattice constant of the stress applying material is greater than that of the channel layer.
    Type: Application
    Filed: August 23, 2021
    Publication date: December 9, 2021
    Inventors: Kai CHENG, Yu ZHU
  • Publication number: 20210376238
    Abstract: A method of manufacturing a phase change memory includes: forming a stacked structure including a conductive layer; a lower electrode layer over the conductive layer; an upper electrode layer over the lower electrode layer; and a phase change material between the lower and upper electrode layers; etching the upper electrode layer according to a first mask to form an upper electrode wire; simultaneously etching the phase change material according to the upper electrode wire and performing a nitridizing treatment in a same plasma etching chamber until a phase change material layer and a nitridized phase change material layer are formed beneath the upper electrode wire and a portion of the lower electrode layer is exposed, wherein the nitridized phase change material layer covers a side surface of the phase change material layer; and removing the portion of the lower electrode layer and the conductive layer therebeneath.
    Type: Application
    Filed: July 22, 2020
    Publication date: December 2, 2021
    Inventors: Chung-Hon LAM, Yu ZHU, Kuo-Feng LO
  • Publication number: 20210376186
    Abstract: A diode structure includes a substrate, a pillar stack disposed on the substrate, and a first barrier layer. The pillar stack includes a first semiconductor layer, a silicon layer, and a second semiconductor layer, in which the first and second semiconductor layers respectively have different dopants such that a conductivity of the first semiconductor layer is different from a conductivity of the second semiconductor layer. The first barrier layer is disposed between the first semiconductor layer and the silicon layer, in which the first barrier layer is configured to prevent the dopants in the first semiconductor layer from diffusing into the silicon layer.
    Type: Application
    Filed: July 17, 2020
    Publication date: December 2, 2021
    Inventors: Kuo-Feng LO, Chung-Hon LAM, Cheng-En WU, Yu ZHU, HAOREN ZHUANG, Yen-Yu HSU
  • Publication number: 20210376110
    Abstract: A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method.
    Type: Application
    Filed: August 13, 2020
    Publication date: December 2, 2021
    Inventors: Chieh-Fang CHEN, Kuo-Feng LO, Chung-Hon LAM, Yu ZHU
  • Publication number: 20210376237
    Abstract: A method of manufacturing a phase change memory includes: forming a stacked structure including a conductive layer, a lower electrode layer over the conductive layer, an upper electrode layer, a phase change material between the lower and upper electrode layers, and a selector material between the conductive layer and the lower electrode layer; etching the upper electrode layer to form an upper electrode wire; etching the phase change material according to the upper electrode wire to form a phase change material layer and expose a portion of the lower electrode layer, wherein the phase change material layer has an exposed side surface; after etching the phase change material, performing a nitridizing treatment on the side surface of the phase change material layer to form a nitridized phase change material layer covering the same; and etching the lower electrode layer, the selector material and the conductive layer.
    Type: Application
    Filed: July 22, 2020
    Publication date: December 2, 2021
    Inventors: Chung-Hon LAM, Yu ZHU, Kuo-Feng LO
  • Publication number: 20210363336
    Abstract: A film, preferably, a multi-layered film, comprising a polymer composition, wherein the polymer composition comprises: within a range from 1 wt % to 25 wt % of a cyclic olefin copolymer based on the weight of the polymer composition, and within a range from 75 wt % to 99 wt % (the remainder of material) of a polyethylene based on the weight of the polymer composition, wherein the cyclic olefin copolymer has a glass transition temperature (Tg) of at least 80° C. The films may be used in shrink packaging application.
    Type: Application
    Filed: April 27, 2018
    Publication date: November 25, 2021
    Inventors: Keran Chen, Yong Yang, Ling Ge, Xiao-Chuan Wang, Zhen-Yu Zhu, LeiLei Ma, Xin Hao Cai, Gregory K. Hall, Caiguo Gong, Jean-Marc C. De Koninck, Robert J. Wittenbrink
  • Patent number: 11182739
    Abstract: A carrier tracking system is applied to a predetermined space. Carriers with optical recognizable marks are operating in the predetermined space, in which each of the optical recognizable mark is associated with information of materials carried by the carrier. The carrier tracking system includes at least one optical capturing device and a computing unit. The at least one optical capturing device is configured to capture images of the predetermined space. The computing unit is configured to determine an optical recognized coordinate of the optical recognizable mark in the images. The computing unit converts the optical recognized coordinate to a real-space coordinate in the predetermined space. In order to locate the carrier, the computing unit further associates the real-space coordinate with the information of materials carried by the carrier.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: November 23, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Zi-Yu Zhu, Choon-Meng Lee
  • Patent number: 11165514
    Abstract: Apparatus and methods for envelope alignment calibration in radio frequency (RF) systems are provided. In certain embodiments, calibration is performed by providing an envelope signal with a peak along an envelope path, and by providing an RF signal with a first peak and a second peak to a power amplifier along an RF signal path. Additionally, an output of the power amplifier is observed to generate an observation signal using an observation receiver. The observation signal includes a first peak and a second peak corresponding to the first peak and the second peak of the RF signal, and a delay between the envelope signal and the RF signal is controlled based on relative size of the peaks of the observation signal to one another.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: November 2, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Florinel G. Balteanu, Yu Zhu, Paul T. DiCarlo
  • Publication number: 20210334442
    Abstract: Provided are a method and system for visualization of a 3D electronic device. The method includes: a structural and/or electrical characteristic of the electronic device is simulated to obtain first visualization data, the electronic device including a semiconductor device and/or an integrated circuit and the first visualization data including 3D grid position information of the electronic device and/or a physical quantity at a grid point; the 3D grid position information and/or physical quantity at the grid point in the first visualization data are/is converted into second visualization data suitable for virtual 3D displaying according to a data type; and the second visualization data is rendered in a virtual space to display a structure and/or physical quantity of the electronic device in the virtual space.
    Type: Application
    Filed: November 26, 2020
    Publication date: October 28, 2021
    Inventors: Yu ZHU, Zhenhua WU
  • Patent number: 11133879
    Abstract: Disclosed is an LTE-V based Internet of Vehicles communication test system and test method. The test system includes an ENodeB base station, a roadside test unit, user test terminal, LTE-V core network and local server group. Mobile communication technology is applied to the field of Internet of Vehicles communication, and two technical schemes are used, i.e., wide-area centralized cellular communication and short-range distributed direct communication corresponding to the network architectures based on access network-user terminal and ProSe direct communication interface, respectively. Not only the communication transmission support with large broadband in wide coverage can be supported, but also to achieve low latency and highly reliable communication services between vehicle and vehicle, vehicle and base station, base station and base station, to meet the needs of road safety and traffic efficiency applications.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 28, 2021
    Assignee: Chang'an University
    Inventors: Xiangmo Zhao, Zhigang Xu, Runmin Wang, Dingbei Liu, Haigen Min, Lan Yang, Yu Zhu, Dongwu Li, Zhanwen Liu
  • Publication number: 20210295595
    Abstract: A method and system for generating a three-dimensional (3D) virtual scene are disclosed. The method includes: identifying a two-dimensional (2D) object in a 2D picture and the position of the 2D object in the 2D picture; obtaining the three-dimensional model of the 3D object corresponding to the 2D object; calculating the corresponding position of the 3D object corresponding to the 2D object in the horizontal plane of the 3D scene according to the position of the 2D object in the picture; and simulating the falling of the model of the 3D object onto the 3D scene from a predetermined height above the 3D scene, wherein the position of the landing point the model of the 3D object in the horizontal plane is the corresponding position of the 3D object in the horizontal plane of the 3D scene.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: HAO CHEN, GUO QIANG HU, QI CHENG LI, LI JUN MEI, JIAN WANG, YI MIN WANG, ZI YU ZHU
  • Publication number: 20210282656
    Abstract: A blood pressure monitoring method, apparatus, and device are provided. The method includes: collecting a first biological signal of a to-be-measured user (S101); and predicting a first blood pressure value of the to-be-measured user based on the first biological signal and a pre-established individual calibration model (102). According to the method, only the first biological signal of the to-be-measured user needs to be collected to predict the first blood pressure value of the to-be-measured user. A collection manner is simple, and sleep of the user is not interrupted, greatly improving user experience.
    Type: Application
    Filed: April 24, 2017
    Publication date: September 16, 2021
    Inventors: Jing LI, Yu ZHU, Wenjuan CHEN
  • Publication number: 20210269787
    Abstract: The present invention provides engineered human alpha-galactosidase polypeptides and compositions thereof. The engineered human alpha-galactosidase polypeptides have been optimized to provide improved thermostability, serum stability, improved cellular uptake, stability under both acidic (pH<4) and basic (pH>7) conditions, reduced immunogenicity, and improved globotriaosylceramide removal from cells. The invention also relates to the use of the compositions comprising the engineered human alpha-galactosidase polypeptides for therapeutic purposes.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 2, 2021
    Inventors: William Casey Hallows, Nikki Dellas, Yu Zhu, Judy Victoria Antonio Viduya, Chinping Chng, Antoinette Sero, Rachel Cathleen Botham, David William Homan, Moulay Hicham Alaoui Ismaili, Jonathan Vroom, Adam P. Silverman, Kristen Jean Vallieu, Charu Shukla Reddy, Kerryn McCluskie
  • Publication number: 20210262834
    Abstract: A five-degree-of-freedom heterodyne grating interferometry system comprises: a single-frequency laser for emitting single-frequency laser light, the single-frequency laser light can be split into a reference light beam and a measurement light beam; an interferometer lens set and a measurement grating for converting the reference light and the measurement light into a reference interference signal and a measurement interference signal; and multiple optical fiber bundles, respectively receiving the measurement interference signal and the reference interference signal, wherein each optical fiber bundle has multiple multi-mode optical fibers respectively receiving interference signals at different positions on the same plane. The measurement system is not over-sensitive to the environment, is small and light, and is easy to arrange.
    Type: Application
    Filed: June 26, 2019
    Publication date: August 26, 2021
    Inventors: Ming ZHANG, Yu ZHU, Fuzhong YANG, Leijie WANG, Rong CHENG, Xin LI, Weinan YE, Jinchun HU