Patents by Inventor YUAN HUANG

YUAN HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096929
    Abstract: A method of making a semiconductor device includes forming a circuit layer over a substrate. The method further includes depositing an insulator over the substrate. The method further includes patterning the insulator to define a test line trench, a first trench, and a second trench, wherein the first trench is on a portion of the substrate exposed by the circuit layer. The method further includes filling the test line trench to define a test line electrically connected to the circuit layer. The method further includes filling the first trench and the second trench to define a capacitor.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Yan-Jhih HUANG, Chun-Yuan HSU, Chien-Chung CHEN, Yung-Hsieh LIN
  • Publication number: 20240096719
    Abstract: A semiconductor device includes a first substrate, an electronic component, and a lid. The first substrate includes a first substrate top side, a first substrate bottom side opposite to the first substrate top side, a first substrate lateral side interposed between the first substrate top side and the first substrate bottom side, and a connector structure. The electronic component is coupled to the first substrate top side and coupled to the connector structure. The lid includes a wall part including a ring part coupled to the first substrate top side, a first part of an overhang part coupled to the first substrate lateral side, and a second part of the overhang part extending from the first part of the overhang part away from the first substrate lateral side.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Chien-Yuan Huang
  • Publication number: 20240093142
    Abstract: The present invention relates to the fields of microorgan-isms, feed, food and ecological restoration, in particular to a strain for degrading deoxynivalenol (DON) and the use thereof. The strain has the deposit number CCTCC No. M 2020565. The strain can grow by means of taking the toxic compound DON as a sole carbon source, and convert the DON into chemical components for itself. The reaction process is irreversible, the reaction conditions are moderate, and secondary pollu-tion cannot be caused. The strain provided in the present invention can be used for preparing a biological detoxification preparation for DON. The strain provided in the present invention can be used for degrading DON in feed and food raw materials, primary processing products, deep processing products and related processing byproducts. The strain provided in the present invention can be applied to various ecosystems such as soil or bodies of water polluted by DON to achieve the purposes of DON degradation and ecological restoration.
    Type: Application
    Filed: November 11, 2021
    Publication date: March 21, 2024
    Inventors: Huiying LUO, Honghai ZHANG, Bin YAO, Huoqing HUANG, Yaru WANG, Yingguo BAI, Xiaoyun SU, Yuan WANG, Tao TU, Jie ZHANG, Huimin YU, Xing QIN, Xiaolu WANG
  • Publication number: 20240095654
    Abstract: Information output methods and apparatuses, computer equipment and readable storage media which relate to the field of computer technology are provided. The information output method includes: detecting whether a search connection is established between a delivery terminal and a beacon device deployed by a target physical object by using a pre-cached joint beacon atlas bound to the target physical object, where the joint beacon atlas records a set of communication identifiers covered by a physical object; if the search connection is established between the delivery terminal and the beacon device deployed by the target physical object, outputting a corresponding time point when the search connection is in a stable state as information of a delivery resource arriving at the target physical object.
    Type: Application
    Filed: December 9, 2021
    Publication date: March 21, 2024
    Inventors: Yun JI, Benshan YOU, Yuan WU, Ping HUANG, Tian HE
  • Publication number: 20240096818
    Abstract: Devices and method for forming a shielding assembly including a first chip package structure sensitive to magnetic interference (MI), a second chip package structure sensitive to electromagnetic interference (EMI), and a shield surrounding sidewalls and top surfaces of the first chip package structure and the second chip package structure, in which the shield is a magnetic shielding material. In some embodiments, the shield may include silicon steel, in some embodiments, the shield may include Mu-metal. The silicon-steel-based or Mu-metal-based shield may provide both EMI and MI protection to multiple chip package structures with various susceptibilities to EMI and MI.
    Type: Application
    Filed: April 20, 2023
    Publication date: March 21, 2024
    Inventors: Harry-Hak-Lay Chuang, Yuan-Jen Lee, Kuo-An Liu, Ching-Huang Wang, C.T. Kuo, Tien-Wei Chiang
  • Patent number: 11931363
    Abstract: A compound of Formula (I), or a pharmaceutically acceptable salt thereof, is provided that has been shown to be useful for treating a PRC2-mediated disease or disorder: wherein R1, R2, R3, R4, R5, and n are as defined herein.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: March 19, 2024
    Assignee: NOVARTIS AG
    Inventors: Ho Man Chan, Xiang-Ju Justin Gu, Ying Huang, Ling Li, Yuan Mi, Wei Qi, Martin Sendzik, Yongfeng Sun, Long Wang, Zhengtian Yu, Hailong Zhang, Ji Yue (Jeff) Zhang, Man Zhang, Qiong Zhang, Kehao Zhao
  • Patent number: 11935871
    Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
  • Patent number: 11935894
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
  • Publication number: 20240086026
    Abstract: Systems and methods are disclosed for providing a virtual mouse for a computing device have a touchscreen. A first placement region of the touchscreen may be determined. The first placement region may then be determined to contain a first portion of at least one touch target. The first portion of the at least one touch target may then be deactivated. A virtual mouse may then be activated at the first placement region.
    Type: Application
    Filed: August 15, 2023
    Publication date: March 14, 2024
    Inventors: Roya CODY, Che YAN, Da Yuan HUANG, Wei LI
  • Publication number: 20240090336
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin YANG, Chung-Te LIN, Sheng-Yuan CHANG, Han-Ting LIN, Chien-Hua HUANG
  • Publication number: 20240090215
    Abstract: The method of forming the semiconductor structure includes the following steps. First trenches and second trenches are respectively formed in a substrate of the logic region and the substrate of the array region. A dielectric liner is formed in the first trenches and second trenches. First coating blocks and second coating blocks are respectively formed in the first trenches and second trenches. A cap layer is formed on the first coating blocks and the second coating blocks. Oxide structures are formed on the cap layer. Part of the oxide structures and part of the cap layer is removed. A semiconductor layer is formed in the array region and disposed on the substrate and between the oxide structures.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Inventors: Yuan-Huang WEI, Chien-Hsien WU, Hsiu-Han LIAO
  • Publication number: 20240086612
    Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
  • Publication number: 20240089607
    Abstract: An image sensing device and a control device of an illumination device thereof are provided. The control device includes a control circuit, an operation circuit, and multiple driving signal generators. The control circuit generates multiple control signals. The operation circuit performs a logical operation on the control signals and an image capturing signal to generate multiple operation results. The driving signal generator respectively provides multiple driving signals to the illumination device according to the operation results, and the driving signals respectively have multiple different output powers.
    Type: Application
    Filed: May 29, 2023
    Publication date: March 14, 2024
    Applicant: HTC Corporation
    Inventors: Chao Shuan Huang, Sheng-Long Wu, Yu-Jui Hsu, Shih-Yao Tsai, Tun-Hao Chao, Sen-Lin Chung, Chih Pin Chung, Chih-Yuan Chien, Shih Hong Sun
  • Publication number: 20240082160
    Abstract: An amlodipine dry suspension, comprising a diluent, a suspending aid, etc. and being free of surfactants. A preparation method therefor comprises the following steps: a) preparing an aqueous mixture 1 containing amlodipine besylate by using a high-speed homogenization method; b) adding sodium benzoate to the mixture 1, and homogenizing same at a high speed to obtain a mixture 2; and c) granulating the mixture 2 and other components, and then drying same. The raw materials are homogenized and mixed at a high speed, no surfactant is added during the preparation, amlodipine is fully wetted by using a high-speed homogenization process, prescription components are simplified, and the amlodipine dry suspension is more suitable for children to use. Compared with ultrasonic stirring, scaled-up and industrial production are easier to realize for the high-speed homogenization process, and at the same time, the preparation is good in stability and convenient to carry.
    Type: Application
    Filed: December 31, 2021
    Publication date: March 14, 2024
    Inventors: Hanxiong Li, Xianzhu Wang, Weitang Chen, Yuan Chen, Ping Guo, Yongyi Wu, Yongmei Qin, Hongxue Huang, Li Wang
  • Patent number: 11929314
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 11930475
    Abstract: A wireless terminal determines a tracking area code (TAC) from a geographic position of the wireless terminal. From the TAC, the wireless terminal determines the tracking area identity based on an indication from the network-side regarding whether or not geographic position based tracking area identity determination is to be used or not. In some implementations, the network-side is a satellite cell that is configured to provide wireless connectivity to the wireless terminal.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: March 12, 2024
    Assignee: ZTE Corporation
    Inventors: Yuan Gao, He Huang, Jianwu Dou
  • Publication number: 20240079230
    Abstract: A plasma-assisted annealing system includes a high temperature furnace, a plasma-induced dissociator and a connecting duct. The plasma-induced dissociator is provided to dissociate a working gas and exhaust the dissociated working gas from its working gas outlet. Both ends of the connecting duct are connected to the working gas outlet of the plasma-induced dissociator and a gas inlet of the high temperature furnace, respectively. The working gas dissociated in the plasma-induced dissociator is introduced into the high temperature furnace via the connecting duct.
    Type: Application
    Filed: December 12, 2022
    Publication date: March 7, 2024
    Inventors: Wei-Chen Tien, Cheng-Yuan Hung, Chang-Sin Ye, Chun-Kai Huang, Yii-Der Wu
  • Publication number: 20240077564
    Abstract: A method of using NC-MRA to generate pelvic veins images and measure rate of blood flow includes subjecting a lay patient to undergo magnetic resonance scan in cooperation with an ECG monitor and a respiration monitor; scanning coronary sections and transverse sections of kidney veins, lower cavity veins, common iliac veins, and external iliac veins to generate two-dimensional images wherein the two-dimensional images use balanced turbo field echo wave sequence; scanning coronary sections of common cardinal veins of abdominal cavity to generate three-dimensional images wherein the three-dimensional images use fast spin-echo short tau inversion recovery wave sequence and sample signals when the ECG monitor monitors myocardial contractility; and using quantification phase-contrast analysis to measure blood flowing through the transverse sections of the veins in a two-dimensional scan.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicant: Chang Gung Memorial Hospital, Chiayi
    Inventors: Chien-Wei Chen, Yao-Kuang Huang, Chung-Yuan Lee, Yeh-Giin Ngo, Yin-Chen Hsu
  • Publication number: 20240078441
    Abstract: A method for knowledge representation and deduction of service logic includes: generating, based on a knowledge representation model, a semantic graph corresponding to conceptual-layer service logic, where the semantic graph includes one or more types of nodes and edges for connecting the one or more types of nodes, and the nodes include at least a node of a variable type; generating, based on the semantic graph and a physical table to which a service object is mapped, an instance graph, where the instance graph includes the nodes and edges in the semantic graph; generating executable code based on a service logic relationship between the nodes in the instance graph; and determining, based on the executable code and a data instance corresponding to a node whose in-degree is 0 in the instance graph, a data instance corresponding to each node in the instance graph.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Inventors: Rong Duan, Kangxing Hu, Wenwen Huang, Yuan Yuan, Wen Peng, Chunxi Liu, Qinjie Yang, Xiaoliang Yin, Shufan Li
  • Patent number: D1018907
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: March 19, 2024
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventors: Yun-Chien Lee, Yi-Ching Hsu, Pei-Yi Lin, Yu-Hung Su, Sheng-Yuan Huang, Chun-Fu Lin