Abstract: A seal ring structure for an integrated circuit includes a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and/or RF circuit block from a noise. A P+ region is provided in a P substrate and positioned under the second portion. A shallow trench isolation (STI) structure surrounds the P+ region and laterally extends underneath a conductive rampart of the second portion.

Abstract: An oscillator circuit, a transceiver, and a method for generating an oscillatory signal are provided to avoid the VCO pulling effect. The oscillator circuit includes an oscillator, a frequency multiplier, a frequency divider, and a mixer module. The oscillator is utilized for generating a first signal having a first frequency. The frequency multiplier is coupled to the oscillator, and utilized for generating a second signal according to the first signal, wherein the second signal has a second frequency. The frequency divider is coupled to the oscillator, and utilized for generating a third signal according to the first signal, wherein the third signal has a third frequency. The mixer module is coupled to the frequency multiplier and the frequency divider, and utilized for mixing the second signal and the third signal to generate the oscillatory signal having an output frequency being not a harmonic of the first frequency.

Abstract: An embodiment of a mixer with carrier leakage self-calibrating is disclosed. The mixer comprises a double balanced mixer, a gm stage comprising a first processing unit and a second processing unit, a current duplicating circuit, a capacitor, a controller and a current compensation unit. The current duplicating circuit selects the first processing unit or the second processing unit and duplicates a duplicated current of the selected processing unit to charge the capacitor. The capacitor has a first terminal and a second terminal, wherein the second terminal is grounded and the first terminal receives the duplicated current. The controller determines a charge time of the capacitor to generate a compensation signal, wherein the charge time is the time that the voltage of the capacitor is charged to equal to a reference voltage. The current compensation unit receives the compensation signal to generate a compensation current to the mixer.

Abstract: The present invention discloses a circuit for settling DC offset and controlling RC time-constant in a direct conversion receiver. The circuit includes a variable resistive unit for providing a continuously or non-continuously variable resistance in the direct conversion receiver. The variable resistive unit can provide the variable resistance by utilizing a controllable transistor or a plurality of resistors. Accordingly, the variable resistive unit can be coupled to a capacitor for constituting a high pass filter, which is capable of rapidly settling DC offset in a direct conversion receiver.

Abstract: A low noise RF mixer is described. The mixer of the present invention has excellent linearity due to reduction of second-order distortion. The mixer includes an inputting stage, a switching stage and a load stage. The inputting stage includes a switching pair and a transconductance circuit. The load stage is formed by resistors. The switching stage includes a switch quad (two switch pairs). Each switch pair of the switching stage has a current source for implementation of current injection to a common source (emitter) junction of the switch pair. For each switch pair of the switching stage, an inductor is connected between the current source and the common source (emitter) junction. In addition, a capacitor is connected with the inductor.

Abstract: An IQ dual mixer for use in radio transmitters and receivers, comprising an in-phase (I) local oscillator transistor pair, a quadrature-phase (Q) local oscillator transistor pair, and a first radio frequency (RF) transistor. The I local oscillator transistor pair is operably coupled to receive an I local oscillator signal and connected in series with a first load pair to output an I product signal. The Q local oscillator transistor pair is operably coupled to receive a Q local oscillator signal and connected in series with a second load pair to output a Q product signal. The first RF transistor has an input terminal coupled to receive a first RF signal. The first RF transistor is coupled in anti-series with each transistor of the I and Q local oscillator transistor pairs.

Abstract: An embodiment of a mixer with carrier leakage self-calibrating is disclosed. The mixer comprises a double balanced mixer, a gm stage comprising a first processing unit and a second processing unit, a current duplicating circuit, a capacitor, a controller and a current compensation unit. The current duplicating circuit selects the first processing unit or the second processing unit and duplicates a duplicated current of the selected processing unit to charge the capacitor. The capacitor has a first terminal and a second terminal, wherein the second terminal is grounded and the first terminal receives the duplicated current. The controller determines a charge time of the capacitor to generate a compensation signal, wherein the charge time is the time that the voltage of the capacitor is charged to equal to a reference voltage. The current compensation unit receives the compensation signal to generate a compensation current to the mixer.

Abstract: A varactor device includes a capacitance circuit having a capacitor set and a first transistor connected across the capacitor set; a first variable resistor; and a second transistor coupled to the first transistor and connected in series to the first variable resistor for feeding an output signal generated by applying voltage to the capacitance circuit back to the first transistor, thereby controlling a gain of the first transistor by tuning the first variable resistor.

Abstract: The present invention sets forth a controllable resistive circuit which comprises a transistor, a capacitor, a charging unit and a discharging unit. The transistor is capable of providing a variable resistance which is controlled to vary continuously and smoothly. The charging and discharging units are used to respectively charge and discharge the capacitor in different periods. As a result, the capacitor can provide a variable voltage which is controlled to vary continuously and smoothly to control the equivalent resistance of the transistor during the period the capacitor is discharging. Therefore, the controllable resistive circuit in accordance with the present invention is capable of being used in any kind of circuit which requires a variable resistance varied continuously and smoothly.

Abstract: A servo loop circuit suitable for DC offset cancellation in a direct conversion receiver. The servo loop in accordance with the present invention has a low pass filtering device with a smoothly and continuously changed corner frequency, so that the response time of the low pass filtering device can be limited to a short period of time without inducing in additional DC offset. The smoothly and continuously changing of the corner frequency is performed by providing a continuously variable resistance by at least one continuously variable resistive unit, which may be implemented by transistor technique. The resistance of the continuously variable resistive unit is continuously varied by smoothly controlling the level of a voltage signal applied thereto.

Abstract: A low noise RF mixer is described. The mixer of the present invention has excellent linearity due to reduction of second-order distortion. The mixer includes an inputting stage, a switching stage and a load stage. The inputting stage includes a switching pair and a transconductance circuit. The load stage is formed by resistors. The switching stage includes a switch quad (two switch pairs). Each switch pair of the switching stage has a current source for implementation of current injection to a common source (emitter) junction of the switch pair. For each switch pair of the switching stage, an inductor is connected between the current source and the common source (emitter) junction. In addition, a capacitor is connected with the inductor.

Abstract: A self DC-bias high frequency logic gate is disclosed. The logic gate comprises at least one input terminal and one output terminal for performing Boolean operation on the high frequency input signals. The logic gate is characterized in that each transistor is coupled to an impedance matching network. The impedance matching network comprises a first terminal and a second terminal. Wherein, the first terminal is coupled to a gate of the transistor, and the second terminal is coupled to a drain of the transistor for providing an operation voltage to the transistor. When a gate of an N-type transistor and a gate of a P-type transistor are coupled with each other, and a drain of the N-type transistor and a drain of the P-type transistor are also coupled with each other, a common impedance matching network is shared with both the N-type transistor and the P-type transistor.

Abstract: An apparatus for removing DC offset and variable gain amplifying simultaneously is provided. A signal voltage level of the output terminal of the first amplifier module is A times that of the first input terminal of the first amplifier module. A voltage level of an output DC offset signal of the first low-pass filter circuit is B times that of the input signal of the first low-pass filter circuit. The output signal of the second amplifier module is a sum of a C1-time amplified first input signal of the second amplifier module and a C2-time amplified second input signal of the second amplifier module, which satisfy the following equation: A×B×C1=?C2.

Abstract: A varactor device includes a capacitance circuit having a capacitor set and a first transistor connected across the capacitor set; a first variable resistor; and a second transistor coupled to the first transistor and connected in series to the first variable resistor for feeding an output signal generated by applying voltage to the capacitance circuit back to the first transistor, thereby controlling a gain of the first transistor by tuning the first variable resistor.

Abstract: A self DC-bias high frequency logic gate is disclosed. The logic gate comprises at least one input terminal and one output terminal for performing Boolean operation on the high frequency input signals. The logic gate is characterized in that each transistor is coupled to an impedance matching network. The impedance matching network comprises a first terminal and a second terminal. Wherein, the first terminal is coupled to a gate of the transistor, and the second terminal is coupled to a drain of the transistor for providing an operation voltage to the transistor. When a gate of an N-type transistor and a gate of a P-type transistor are coupled with each other, and a drain of the N-type transistor and a drain of the P-type transistor are also coupled with each other, a common impedance matching network is shared with both the N-type transistor and the P-type transistor.

Abstract: A loading circuit capable of canceling a DC offset and a mixer using the same. The loading circuit includes a first current mirror unit and a second current mirror unit for respectively receiving a first input signal and a second input signal and generating a first signal current and a second signal current proportional to the first and second input signals, a first compensation unit and a second compensation unit for respectively receiving the first and second input signals, filtering AC components of the input signals, and generating a first compensation current and a second compensation current proportional to the DC components of the first and second input signals, a first loading unit for receiving the first signal current and the second compensation current and generating a first output signal, and a second loading unit for receiving the second signal current and the first compensation current and generating a second output signal.

Abstract: A loading circuit capable of canceling a DC offset and a mixer using the same. The loading circuit includes a first current mirror unit and a second current mirror unit for respectively receiving a first input signal and a second input signal and generating a first signal current and a second signal current proportional to the first and second input signals, a first compensation unit and a second compensation unit for respectively receiving the first and second input signals, filtering AC components of the input signals, and generating a first compensation current and a second compensation current proportional to the DC components of the first and second input signals, a first loading unit for receiving the first signal current and the second compensation current and generating a first output signal, and a second loading unit for receiving the second signal current and the first compensation current and generating a second output signal.

Abstract: An apparatus for removing DC offset and variable gain amplifying simultaneously is provided. A signal voltage level of the output terminal of the first amplifier module is A times that of the first input terminal of the first amplifier module. A voltage level of an output DC offset signal of the first low-pass filter circuit is B times that of the input signal of the first low-pass filter circuit. The output signal of the second amplifier module is a sum of a C1-time amplified first input signal of the second amplifier module and a C2-time amplified second input signal of the second amplifier module, which satisfy the following equation: A×B×C1=?C2.

Abstract: A method of manufacturing a thin film transistor for solving the drawbacks of the prior arts is disclosed. The method includes steps of providing an insulating substrate, sequentially forming a source/drain layer, a primary gate insulating layer, and a first conducting layer on the insulating substrate, etching the first conducting layer to form a primary gate; sequentially forming a secondary gate insulating layer and a second conducting layer on the primary gate; and etching the second conducting layer to form a first secondary gate and a second secondary gate.

Abstract: A method of manufacturing a thin film transistor for solving the drawbacks of the prior art is disclosed. The method includes steps of providing an insulating substrate, sequentially forming a source/drain layer, a primary gate insulating layer, and a first conducting layer on the insulating substrate, etching the first conducting layer to form a primary gate; sequentially forming a secondary gate insulating layer and a second conducting layer on the primary gate; and etching the second conducting layer to form a first secondary gate and a second secondary gate.