Patents by Inventor Yuan Wen

Yuan Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7974053
    Abstract: An ESD protection circuit for a differential I/O pair is provided. The circuit includes an ESD detection circuit, a discharge device, and four diodes. The first diode is coupled between the first I/O pin and the discharge device in a forward direction toward the discharge device. The second diode is coupled between the second I/O pin and the discharge device in a forward direction toward the second I/O pin. The third diode is coupled between the discharge device and the positive power line in a forward direction toward the positive power line. The fourth diode is coupled between the discharge device and the negative power line in a forward direction toward the discharge device. Via an output end, the ESD detection circuit triggers the discharge device during ESD events.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: July 5, 2011
    Assignee: Amazing Microelectronic Corp
    Inventors: Ming-Dou Ker, Yuan-Wen Hsiao, Hsin-Chin Jiang
  • Publication number: 20110151669
    Abstract: A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventors: Ting-Yi Lin, Chi-Yuan Wen, Chuang Tse Chuan, Miau-Shing Tsay, Ming Li Wu
  • Publication number: 20110147338
    Abstract: A method of forming an integrated circuit structure on a wafer includes providing an etcher having an electrostatic chuck (ESC); and placing the wafer on the ESC. The wafer includes a conductive feature and a dielectric layer over the conductive feature. The method further includes forming and patterning a photo resist over the wafer; and etching the dielectric layer to form a via opening in the wafer using the etcher. An ashing is performed to the photo resist to remove the photo resist. An oxygen neutralization is performed to the wafer. A de-chuck step is performed to release the wafer from the ESC.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventors: Ting-Yi Lin, Chi-Yuan Wen
  • Publication number: 20110142844
    Abstract: Human antibodies and antigen-binding portions of those antibodies that specifically bind extended Type I chain glycosphingolipids are provided.
    Type: Application
    Filed: September 7, 2008
    Publication date: June 16, 2011
    Applicant: GLYCONEX INC.
    Inventors: Tong-Hsuan Chang, Jerry Ting, Tsai-Hsia Hong, Mei-Chun Yang, Liahng-Yirn Liu, Shu-Yen Chang, Ying-Jin Chen, Jaw-Yuan Wen, Kazuko Handa, Sen-itiroh Hakomori
  • Patent number: 7889470
    Abstract: An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: February 15, 2011
    Assignee: Amazing Microelectronic Corp.
    Inventors: Ming-Dou Ker, Yuan-Wen Hsiao, Ryan Hsin-Chin Jiang
  • Publication number: 20110024525
    Abstract: A perfume bottle spray head assembly is disclosed to include a nozzle head, a lock cap, a receptacle, a plug, a dip tube, an outer cap and a rotary shut-off control plate. The nozzle head has passage means defined therein to facilitate mixing of liquid perfume with compressed air for enabling well-mixed liquid perfume and compressed air mixture to be sprayed out in a mist. The rotary shut-off control plate is operable to rotate the plug in the receptacle between a close position to shut off the liquid perfume passage and an open position to open the liquid perfume passage.
    Type: Application
    Filed: July 29, 2009
    Publication date: February 3, 2011
    Applicant: ING WEN PRECISION ENT. CO., LTD.
    Inventor: Yuan-Wen Yu
  • Patent number: 7880195
    Abstract: An ESD protection device comprises a P-type substrate, a first substrate-triggered silicon controlled rectifiers (STSCR) disposed in the P-type substrate and a second STSCR disposed in the P-type substrate. The first STSCR comprises a first N-well, a first P-well, a first N+ diffusion region, a first P+ diffusion region, and a first trigger node. The second STSCR comprises a second N-well electrically connected to the first N-well, a second P-well electrically connected to the first P-well, a second N+ diffusion region electrically connected to the first P+ diffusion region, a second P+ diffusion region electrically connected to the first N+ diffusion region, and a second trigger node. A layout area of an integrated circuit and a pin-to-pin ESD current path can be reduced.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: February 1, 2011
    Assignees: United Microelectronics Corp., National Chiao-Tung University
    Inventors: Ming-Dou Ker, Yuan-Wen Hsiao, Chang-Tzu Wang
  • Publication number: 20100279073
    Abstract: A housing for an electronic device is disclosed, the housing comprises a base layer and a transparent film layer overlapped in the base layer, the film layer includes an inner surface abutting the base layer and an outer surface having ridges protruding thereform. The housing is formed by injection molding a molten plastic material over the transparent film layer, the ridges are formed on the transparent film layer by the molten plastic pressing the transparent film layer in injection molding. It is also disclosed a mold for making the housing and a method to make the housing.
    Type: Application
    Filed: December 10, 2009
    Publication date: November 4, 2010
    Applicants: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventors: BEN-DING TSAO, WEN-LIN XIONG, QI-QUAN YAN, YUE-JUN HE, MAN-XIANG DUAN, SAN-YUAN WEN
  • Publication number: 20100277926
    Abstract: A light guiding diffuser used for assembling with a light emitting diode module to form an illuminating light source. The light guiding diffuser includes an elliptical ring-shaped base portion and a convex portion extended from a surface of the base portion and formed a space with the base portion for accommodating the light emitting diode module. The convex portion has a cross section which has a minimum thickness in a center thereof and the thickness of the cross section continuous increases from the center toward the base portion.
    Type: Application
    Filed: May 4, 2009
    Publication date: November 4, 2010
    Inventor: Fong-Yuan WEN
  • Patent number: 7817386
    Abstract: An ESD protection circuit suitable for applying in an integrated circuit with separated power domains is provided. The circuit includes a P-type MOSFET coupled between a first circuit in a first power domain and a second circuit in a second power domain. A source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. A gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. A drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. A body terminal of the P-type MOSFET is also coupled to the connection node.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: October 19, 2010
    Assignee: Amazing Microelectronics Corp.
    Inventors: Ming-Dou Ker, Yuan-Wen Hsiao, Ryan Hsin-Chin Jiang
  • Publication number: 20100254140
    Abstract: A lamp holder of a LED streetlamp includes a lamp cover, a LED unit and a plurality of heat-conducting posts. The LED unit is provided below the lamp cover. A transparent lamp cover covers outside the LED unit. Further, the heat-conducting posts are arranged upright in the lamp cover and separated from each other by a distance. Each of the heat-conducting posts is connected to the inner edge surface of the lamp cover opposite to the LED unit and extends toward the top edge of the lamp cover to be located between the top and bottom of the lamp cover. On both sides of the lamp cover laterally facing the heat-conducting posts, venting holes are provided to form an open structure, thereby allowing outside air to enter the lamp cover and flow among the heat-conducting posts.
    Type: Application
    Filed: April 7, 2009
    Publication date: October 7, 2010
    Inventors: Fong-Yuan WEN, Hung-Tsung HSU
  • Patent number: 7772824
    Abstract: A control method for adjusting leading edge blanking time in a power converting system is disclosed. The control method includes: receiving a feedback signal relative to a load connected to an output terminal of the power converting system; determining the leading edge blanking time to be a first value if the feedback signal has a magnitude about a first voltage; and determining the leading edge blanking time to be a second value if the feedback signal has a magnitude about a second voltage, wherein the first value is smaller than the second value, and the first voltage is greater than the second voltage.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: August 10, 2010
    Assignee: Leadtrend Technology Corp.
    Inventors: Yuan-Wen Chang, Yu-Bin Wang, Ming-Nan Chuang, Yu-Chuan Liu
  • Publication number: 20100178930
    Abstract: A positioning method is provided, particularly adaptable for a mobile device. Satellite signals are first received from at least one satellites. At least one first search process is performed on the satellite signals by using an adjustable integration time. A tracking process is then performed when the at least one satellite is acquired in the at least one search process.
    Type: Application
    Filed: January 13, 2009
    Publication date: July 15, 2010
    Applicant: MEDIATEK INC.
    Inventors: Hsin-Chung Yeh, Yuan Wen Ting
  • Publication number: 20100157596
    Abstract: A low-profile light-emitting diode (LED) lamp includes a base, a cover, a heat dissipation plate, an LED module, a circuit board, and a light guide hood. The base and the cover respectively form a base opening and a cover opening. The base and the cover include a recess-projection mating structure therebetween to form an outer water sealing wall and an inner water sealing wall that surround the base opening and the cover opening. The light guide hood, the circuit board, and the LED module are arranged inside the inner water sealing wall. The base and the cover are fixed together through recess-projection mating formed between posts and holes to also realize water resistance. The heat generated by the LED module is dissipated by the heat dissipation plate, which is set on an outer surface of the base and is provided with a plurality of convection chambers that induce heat convection.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 24, 2010
    Applicant: CROWNMATE TECHNOLOGY CO., LTD.
    Inventors: Fong-Yuan Wen, Li-Hsin Chou
  • Publication number: 20100150427
    Abstract: A portable wafer inspection system is applied on an inspection window of a manufacturing tool for wafers. The portable wafer inspection system comprises: a housing, a lighting unit, and an inspection unit. The housing has a receiving room therein, and a plurality of fixing members is disposed at the opening of the housing. The fixing members are used for fixing the housing on the inspection window of the manufacturing tool. The lighting unit and the inspection unit are disposed in the receiving room of the housing, wherein the inspection unit is for capturing images of the wafers.
    Type: Application
    Filed: April 22, 2009
    Publication date: June 17, 2010
    Applicant: INOTERA MEMORIES, INC.
    Inventors: YUAN WEN LIU, HUNG CHIH KUO, CHENG FA TSAO
  • Publication number: 20100142107
    Abstract: An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.
    Type: Application
    Filed: February 1, 2010
    Publication date: June 10, 2010
    Inventors: Ming-Dou Ker, Yuan-Wen Hsiao, Ryan Hsin-Chin Jiang
  • Publication number: 20100140659
    Abstract: An ESD protection device comprises a P-type substrate, a first substrate-triggered silicon controlled rectifiers (STSCR) disposed in the P-type substrate and a second STSCR disposed in the P-type substrate. The first STSCR comprises a first N-well, a first P-well, a first N+ diffusion region, a first P+ diffusion region, and a first trigger node. The second STSCR comprises a second N-well electrically connected to the first N-well, a second P-well electrically connected to the first P-well, a second N+ diffusion region electrically connected to the first P+ diffusion region, a second P+ diffusion region electrically connected to the first N+ diffusion region, and a second trigger node. A layout area of an integrated circuit and a pin-to-pin ESD current path can be reduced.
    Type: Application
    Filed: December 8, 2008
    Publication date: June 10, 2010
    Inventors: Ming-Dou Ker, Yuan-Wen Hsiao, Chang-Tzu Wang
  • Publication number: 20100124084
    Abstract: A control circuit for use in a power converter has a multi-function terminal, a current comparator circuit, and an under-voltage detection circuit. The current comparator circuit compares current flowing through a power switch of the power converter with a reference value through the multi-function terminal when the power switch is on, and turns the power switch off when the current reaches the reference value. The under-voltage detection circuit determines whether an input voltage of the power converter is less than a predetermined value through the multi-function terminal when the power switch is turned off.
    Type: Application
    Filed: November 18, 2008
    Publication date: May 20, 2010
    Inventors: Yuan-Wen Chang, Chun-Teh Chen, Ren-Yi Chen, Yi-Shan Chu
  • Patent number: 7711118
    Abstract: The security system for a protected object comprises a first wireless module, a central controller, and a remote authorization server. The first wireless module and the central controller are disposed in the protected object. The first wireless module transmits an authorization request with an authorization ID (identification) of the protected object, and receives an authorization response. The central controller is coupled to the first wireless module, and allows the protected object to operate in accordance with the authorization response. The remote authorization server, responsive to the authorization request, generates the authorization response from an authorization record thereof in accordance with the authorization ID, and transmits the authorization response.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: May 4, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Yuh-Fwu Chou, Hsin-Hsien Yeh, Mo-Hua Yang, Horng-Yuan Wen, Jing-Pin Pan, Ying-Chang Hung
  • Patent number: D630520
    Type: Grant
    Filed: January 24, 2010
    Date of Patent: January 11, 2011
    Assignee: Ing Wen Precision Ent. Co., Ltd.
    Inventor: Yuan-Wen Yu