Abstract: A semiconductor device of an embodiment includes a SiC layer having a surface, the surface inclined at an angle of 0° to 10° with respect to a {000-1} face or the surface having a normal line direction inclined at an angle of 80° to 90° with respect to a <000-1> direction, a gate electrode, a gate insulating layer provided between the surface and the gate electrode, and a region provided between the surface and the gate insulating layer, a maximum concentration of deuterium (D) in the region being 1×1020 cm?3 or more and a maximum concentration of hydrogen (H) in the region being 1×1019 cm?3 or less.

Abstract: A memory system according to an embodiment may have an integration unit and a prediction unit. The integration unit may detect substrate current flowing through a substrate of a non-volatile memory when the non-volatile memory with a memory cell which has binary or multivalued being the binary or more is written/erased. The integration unit may records an integration value of the detected substrate current into a storage. The prediction unit may predict a lifetime of the non-volatile memory based on the integration value which is recorded on the storage.

Abstract: According to an embodiment, a decoding device includes a variable node processor, a check node processor, a first forwarder, and a second forwarder. The variable node processor is configured to perform variable node processing on variable nodes defined by a code and output first messages. The check node processor is configured to perform check node processing on check nodes defined by the code based on the first messages and output second messages. The first forwarder is configured to forward one or more first messages remaining after excluding messages to be forwarded to one or more check nodes corresponding to one or more of the second messages having been stored in ae storage, to the check nodes. The second forwarder is configured to forward the second messages to the variable nodes and forward the one or more of the second messages to the storage.

Abstract: According to an embodiment, a semiconductor device includes an error corrector, a read controller, and a majority processor. The error corrector is configured to perform error correction on data read from a storage, and output the number of errors contained in the data when errors cannot be corrected by the error correction. The read controller is configured to read pieces of data from a first address in the storage according to respective read conditions, select, from the read conditions, a read condition corresponding to a smallest of the numbers of errors obtained by the error correction performed on the pieces of data corresponding to the respective read conditions, and perform reading from the first address multiple times according to the selected read condition. The majority processor is configured to perform a majority process between a plurality of pieces of data obtained by the multiple times of reading.

Abstract: According to an embodiment, an information processing system includes a time constant processor and a pattern generator. The time constant processor binarizes values indicating a plurality of unit circuits each including a gate insulating film on the basis of a time to emission indicating a time from when a defect in the gate insulating film captures a carrier in a channel current caused to flow by application of a gate voltage to the unit circuits to when the defect emits the carrier. The pattern generator generates a pattern unique to the unit circuits using the values indicating the respective unit circuits binarized by the time constant processor.

Abstract: A nonvolatile semiconductor memory according to an embodiment includes: a semiconductor region; a first insulating film formed on the semiconductor region; a charge storage film formed on the first insulating film; a hydrogen diffusion preventing film formed on the charge storage film; a second insulating film formed on the hydrogen diffusion preventing film; a control gate electrode formed on the second insulating film; a hydrogen discharge film formed on the control gate electrode; and a sidewall formed on a side surface of a multilayer structure including the first insulating film, the charge storage film, the hydrogen diffusion preventing film, the second insulating film, and the control gate electrode, the sidewall containing a material for preventing hydrogen from diffusing.

Abstract: According to an embodiment, an imaging element includes a plurality of light receiving elements, a plurality of scanning circuits, a first line comprising a plurality of nodes, and a plurality of first variable resistance elements. The plurality of scanning circuits are respectively connected to the plurality of light receiving elements. Each of the plurality of first variable resistance elements is connected between the corresponding one of the nodes and a corresponding one of the scanning circuits. At least one of the first variable resistance elements includes a plurality of resistance elements connected to each other in parallel.

Abstract: According to an embodiment, a decoding device includes a check node processor, and a converter. The probability acquirer is configured to acquire. The check node processor is configured to perform check node processing during in a decoding operation of encoded data. A probability value for each bit of the encoded data is treated as an initial variable node in the check node processing. The converter is configured to convert, into bit values, updated values of the probability values based on the check node processing. The check node processor includes a check node circuit having a topology corresponding to a two-state trellis diagram representing the check node processing. The check node circuit includes conducting wires each corresponding to an edge of the two-state trellis diagram and includes switch units which are arranged on the conducting wires and switching of which is controlled according to a predetermined probability.

Abstract: According to an embodiment, an authentication system includes a physical device, a calculator, and an authenticator. The physical device includes a data source which outputs a data sequence along time series. The calculator performs, using hidden Markov model, probability calculation on an ID which is based on the data sequence obtained from the physical device. The authenticator authenticates the physical device based on calculation result of the calculator.

Abstract: According to an embodiment, a memory system includes a memory and a computation unit. Into the memory, data are written. The memory stores therein multiple check matrices. Each of the check matrices is associated with the number of errors in the written data. The computation unit is configured to perform a first error correction on the written data by selectively using, from among the check matrices, a check matrix associated with the number of errors recognized in the written data.

Abstract: This semiconductor device comprises: a gate insulating film provided on a surface of a channel layer; a gate electrode provided on an upper surface of the gate insulating film; and a diffusion layer provided in the channel layer. Furthermore, this semiconductor device comprises: a polycrystalline silicon film provided so as to cover a surface of the gate electrode and the diffusion layer; and an inter-layer insulating film provided so as to cover the gate electrode and the polycrystalline silicon film.

Abstract: A memory system according to embodiments comprises a memory chip that includes a memory cell array having a plurality of memory cells, a first writing unit that writes first data in a first memory cell in the memory cell array, and a second writing unit that writes second data in a second memory cell which is adjacent to the first memory cell. The second data is used in adjusting a threshold value of the first memory cell.

Abstract: According to an embodiment, a semiconductor storage device includes a first storage unit, a read control unit, a second storage unit, and a write control unit. The first storage unit is configured to store data supplied from a host device. The read control unit is configured to perform control of reading the data in accordance with a read request. The second storage unit is configured to store a logical address used for reading the data from the first storage unit by the read control unit. The write control unit is configured to perform control of adding the stored logical address to the data and write the resulting data into the first storage unit in a case where a size of the data requested to be written into the first storage unit by the host device is smaller than a threshold.

Abstract: According to one embodiment, a resistance change device includes a first electrode including a metal, a second electrode, and an amorphous oxide layer including Si and O between the first and second electrode, the layer having a concentration gradient of O and a first peak thereof in a direction from the first electrode to the second electrode.

Abstract: A memory system according to embodiments comprises a memory chip that includes a memory cell array having a plurality of memory cells, a first writing unit that writes first data in a first memory cell in the memory cell array, and a second writing unit that writes second data in a second memory cell which is adjacent to the first memory cell. The second data is used in adjusting a threshold value of the first memory cell.

Abstract: According to an embodiment, a semiconductor storage device includes a first storage unit, a read control unit, a second storage unit, and a write control unit. The first storage unit is configured to store data supplied from a host device. The read control unit is configured to perform control of reading the data in accordance with a read request. The second storage unit is configured to store a logical address used for reading the data from the first storage unit by the read control unit. The write control unit is configured to perform control of adding the stored logical address to the data and write the resulting data into the first storage unit in a case where a size of the data requested to be written into the first storage unit by the host device is smaller than a threshold.

Abstract: A semiconductor device according to an embodiment comprises: a gate insulating film formed on a semiconductor substrate; a semiconductor layer formed on the gate insulating film; and a first metal layer formed to be electrically connected to the semiconductor layer. 1×1019 atoms/cm3 or more of a Group VI element exists in an interface of the semiconductor layer and the first metal layer.

Abstract: According to an embodiment, a semiconductor circuit includes a substrate, a tunnel oxide film, a charge storage film, a blocking layer, and plural nodes. The substrate is made of a semiconductor in which two diffusion layers each serving as either a source or a drain are formed. The tunnel oxide film is formed on a region of the substrate between the diffusion layers. The charge storage film is formed on the tunnel oxide layer and stores charge. The blocking layer is formed between the charge storage film and a gate electrode and has layers of a first oxide film, a nitride film and a second oxide film to have a thickness of 5 nm or larger but 15 nm or smaller. The nodes allow external application of voltages so that the source and the drain are reversed and allow detection a gate voltage, a drain current and a substrate current.

Abstract: According to one embodiment, an information recording device includes first and second electrodes, a variable resistance layer between the first and second electrodes, and a control circuit which controls the variable resistance layer to n (n is a natural number except 1) kinds of resistance. The variable resistance layer comprises a material filled between the first and second electrodes, and particles arranged in a first direction from the first electrode to the second electrode in the material, and each of the particles has a resistance lower than that of the material. A resistance of the variable resistance layer is decided by a short between the first electrode and at least one of the particles.

Abstract: According to one embodiment, a resistance change device includes a first electrode including a metal, a second electrode, and an amorphous oxide layer including Si and O between the first and second electrode, the layer having a concentration gradient of O and a first peak thereof in a direction from the first electrode to the second electrode.