Patents by Inventor Yuichiro Mitani
Yuichiro Mitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100250223Abstract: A semiconductor circuit deterioration simulation method for a circuit including MOSFETs includes inserting a dynamic voltage source associated with a fluctuation in voltage/current characteristics into each gate terminal of a plurality of MOSFETs in series, calculating dynamic deterioration amounts of the plurality of MOSFETs by performing circuit simulation and calculating a dynamic deterioration amount, and repeating the above processing to perform the circuit deterioration simulation over the long term.Type: ApplicationFiled: January 5, 2010Publication date: September 30, 2010Inventors: Daisuke Hagishima, Kazuya Matsuzawa, Yuichiro Mitani, Shigeto Fukatsu, Kouichirou Inoue
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Publication number: 20100244157Abstract: A semiconductor device includes a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having sites that capture or release charges formed by inclusion of the element, density of the element in the metal oxide layer being in the range of 1×1015 cm?3 to 2.96×1020 cm?3, the sites being distributed to have a peak closer to the semiconductor region than to a center of the metal oxide layer; and a gate electrode formed on the gate insulating film.Type: ApplicationFiled: February 23, 2010Publication date: September 30, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Izumi HIRANO, Yuichiro Mitani, Tatsuo Shimizu, Yasushi Nakasaki, Akiko Masada, Shigeto Fukatsu, Masahiro Koike
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Patent number: 7772129Abstract: It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.Type: GrantFiled: August 28, 2006Date of Patent: August 10, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Matsushita, Koichi Muraoka, Koichi Kato, Yasushi Nakasaki, Yuichiro Mitani
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Patent number: 7749919Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.Type: GrantFiled: September 6, 2007Date of Patent: July 6, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Kiwamu Sakuma, Daisuke Matsushita, Koichi Kato, Yasushi Nakasaki, Izumi Hirano, Kouichi Muraoka, Yuichiro Mitani, Shigeto Fukatsu, Toshihide Ito
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Publication number: 20100052039Abstract: A semiconductor device of an embodiment can prevent nitriding of the lower-layer insulating film and oxygen diffusion from the upper-layer insulating film, so as to minimize the decrease in charge capture density. This semiconductor device includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a nitrogen-added amorphous silicon layer formed on the first insulating film, a first silicon nitride layer formed on the amorphous silicon layer, and a second insulating film formed above the first silicon nitride layer.Type: ApplicationFiled: July 23, 2009Publication date: March 4, 2010Inventors: Daisuke MATSUSHITA, Yuichiro MITANI
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Publication number: 20100052035Abstract: A nonvolatile semiconductor memory apparatus includes: a source and drain regions formed at a distance from each other in a semiconductor layer; a first insulating film formed on the semiconductor layer located between the source region and the drain region, the first insulating film including a first insulating layer and a second insulating layer formed on the first insulating layer and having a higher dielectric constant than the first insulating layer, the second insulating layer having a first site performing hole trapping and releasing, the first site being formed by adding an element different from a base material to the second insulating film, the first site being located at a lower level than a Fermi level of a material forming the semiconductor layer; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.Type: ApplicationFiled: March 13, 2009Publication date: March 4, 2010Inventors: Masahiro KOIKE, Yuichiro Mitani, Tatsuo Shimizu, Naoki Yasuda, Yasushi Nakasaki, Akira Nishiyama
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Publication number: 20100041193Abstract: A nonvolatile semiconductor memory device includes a floating gate electrode which is selectively formed on a main surface of a first conductivity type with a first gate insulating film interposed therebetween, a control gate electrode formed on the floating gate electrode with a second gate insulating film interposed therebetween, and source/drain regions of a second conductivity type which are formed in the main surface of the substrate in correspondence with the respective gate electrodes. The first gate electrode has a three-layer structure in which a silicon nitride film is held between silicon oxide films, and the silicon nitride film includes triple coordinate nitrogen bonds.Type: ApplicationFiled: October 23, 2009Publication date: February 18, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Yuichiro Mitani, Daisuke Matsushita
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Patent number: 7619274Abstract: A nonvolatile semiconductor memory device includes a floating gate electrode which is selectively formed on a main surface of a first conductivity type with a first gate insulating film interposed therebetween, a control gate electrode formed on the floating gate electrode with a second gate insulating film interposed therebetween, and source/drain regions of a second conductivity type which are formed in the main surface of the substrate in correspondence with the respective gate electrodes. The first gate electrode has a three-layer structure in which a silicon nitride film is held between silicon oxide films, and the silicon nitride film includes triple coordinate nitrogen bonds.Type: GrantFiled: March 18, 2005Date of Patent: November 17, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yuichiro Mitani, Daisuke Matsushita
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Patent number: 7586163Abstract: A semiconductor device includes a semiconductor substrate; an insulation film provided on the semiconductor substrate; and an electrode provided on the insulation film, and containing boron and a semiconductor material, wherein at least one element of the group V and carbon is introduced into an interface between the insulation film and the electrode.Type: GrantFiled: November 28, 2005Date of Patent: September 8, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Kato, Daisuke Matsushita, Koichi Muraoka, Yasushi Nakasaki, Yuichiro Mitani, Nobutoshi Aoki
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Publication number: 20080305647Abstract: It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.Type: ApplicationFiled: August 28, 2006Publication date: December 11, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daisuke Matsushita, Koichi Muraoka, Koichi Kato, Yasushi Nakasaki, Yuichiro Mitani
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Publication number: 20080173927Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.Type: ApplicationFiled: September 6, 2007Publication date: July 24, 2008Inventors: Kiwamu Sakuma, Daisuke Matsushita, Koichi Kato, Yasushi Nakasaki, Izumi Hirano, Kouichi Muraoka, Yuichiro Mitani, Shigeto Fukatsu, Toshihide Ito
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Publication number: 20080135922Abstract: A nonvolatile semiconductor memory device includes: a memory element, the memory element including: a semiconductor substrate; a first insulating film formed on a region in the semiconductor substrate located between a source region and a drain region, and having a stack structure formed with a first insulating layer, a second insulating layer, and a third insulating layer in this order, the first insulating layer including an electron trapping site, the second insulating layer not including the electron trapping site, and the third insulating layer including the electron trapping site, and the electron trapping site being located in a position lower than conduction band minimum of the first through third insulating layers while being located in a position higher than conduction band minimum of a material forming the semiconductor substrate; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second iType: ApplicationFiled: September 13, 2007Publication date: June 12, 2008Inventors: Yuichiro Mitani, Masahiro Koike, Yasushi Nakasaki, Daisuke Matsushita
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Patent number: 7372113Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.Type: GrantFiled: July 1, 2004Date of Patent: May 13, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
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Patent number: 7279737Abstract: A nonvolatile semiconductor memory device includes a gate electrode portion composed of a floating gate electrode formed above a main surface of a semiconductor substrate of a first conductivity type via a tunnel insulating film, an inter-electrode insulating film formed on the floating gate electrode and formed of a stacked structure film of three or more layers formed of two or more types of high-dielectric material, and a control gate electrode formed above the floating gate electrode via the inter-electrode insulating film, and source and drain regions of a second conductivity type which are formed on the main surface of the substrate with the gate electrode portion being arranged between the source and drain regions.Type: GrantFiled: March 14, 2005Date of Patent: October 9, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Akiko Nara, Masahiro Koike, Yuichiro Mitani
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Publication number: 20070215958Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.Type: ApplicationFiled: May 15, 2007Publication date: September 20, 2007Applicant: Kabushiki Kaisha ToshibaInventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
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Publication number: 20060278940Abstract: A semiconductor device includes a semiconductor substrate; an insulation film provided on the semiconductor substrate; and an electrode provided on the insulation film, and containing boron and a semiconductor material, wherein at least one element of the group V and carbon is introduced into an interface between the insulation film and the electrode.Type: ApplicationFiled: November 28, 2005Publication date: December 14, 2006Inventors: Koichi Kato, Daisuke Matsushita, Koichi Muraoka, Yasushi Nakasaki, Yuichiro Mitani, Nobutoshi Aoki
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Patent number: 7109103Abstract: A semiconductor device including a silicon substrate, a gate insulator film formed on the silicon substrate and including silicon, deuterium, and at least one of oxygen and nitrogen, and a gate electrode formed on the gate insulator film wherein a deuterium concentration in a vicinity of an interface of the gate insulator film with the gate electrode is at least 1×1017 cm?3, and a deuterium concentration in a vicinity of an interface of the gate insulator film with the silicon substrate is higher than the deuterium concentration in the vicinity of the interface of the gate insulation film with the gate electrode.Type: GrantFiled: June 22, 2004Date of Patent: September 19, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Yuichiro Mitani, Hideki Satake
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Patent number: 7015121Abstract: A method of manufacturing a semiconductor device comprises a step of depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by epitaxial growth on an amorphous semiconductor layer, a step of depositing a second amorphous semiconductor layer on the crystalline insulating layer, a step of growing said first and second semiconductor layers into a polycrystal or single crystal layer in a solid phase, using said crystalline insulating film as core, and a step of forming a functional element containing said first and second semiconductor layer.Type: GrantFiled: August 4, 2004Date of Patent: March 21, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Yuichiro Mitani, Yukie Nishikawa
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Publication number: 20050285180Abstract: A nonvolatile semiconductor memory device includes a floating gate electrode which is selectively formed on a main surface of a first conductivity type with a first gate insulating film interposed therebetween, a control gate electrode formed on the floating gate electrode with a second gate insulating film interposed therebetween, and source/drain regions of a second conductivity type which are formed in the main surface of the substrate in correspondence with the respective gate electrodes. The first gate electrode has a three-layer structure in which a silicon nitride film is held between silicon oxide films, and the silicon nitride film includes triple coordinate nitrogen bonds.Type: ApplicationFiled: March 18, 2005Publication date: December 29, 2005Inventors: Yuichiro Mitani, Daisuke Matsushita
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Publication number: 20050275012Abstract: A nonvolatile semiconductor memory device includes a gate electrode portion composed of a floating gate electrode formed above a main surface of a semiconductor substrate of a first conductivity type via a tunnel insulating film, an inter-electrode insulating film formed on the floating gate electrode and formed of a stacked structure film of three or more layers formed of two or more types of high-dielectric material, and a control gate electrode formed above the floating gate electrode via the inter-electrode insulating film, and source and drain regions of a second conductivity type which are formed on the main surface of the substrate with the gate electrode portion being arranged between the source and drain regions.Type: ApplicationFiled: March 14, 2005Publication date: December 15, 2005Inventors: Akiko Nara, Masahiro Koike, Yuichiro Mitani