Abstract: A semiconductor memory device includes first and second bit lines, memory cells each including first and second storage nodes, which are connected through selecting transistors to the first and second bit lines, respectively, a pre-charge circuit configured to pre-charge the first and second bit lines to a predetermined potential so as to read data, a hold circuit configured to maintain a potential level of the first and second bit lines, a read circuit connected to the first bit line, and a leak circuit having one terminal connected to the second bit line and another terminal connected to a ground. The leak circuit allows a current to leak from the second bit line.

Abstract: A semiconductor memory device comprising: a memory array including a plurality of memory cells; a plurality of word lines corresponding to the respective memory cells; a pair of local bit lines corresponding to the memory array; a pair of global bit lines corresponding to the pair of local bit lines; a precharge circuit including an output terminal being connected to the pair of local bit lines; a local write amplifier circuit including a data input terminal being connected to the pair of global bit lines and an output terminal being connected to the pair of local bit lines; and a control signal line being connected to an input terminal of the precharge circuit and to a control input terminal of the local write amplifier circuit, wherein the local write amplifier circuit is deactivated by the control signal line when the precharge circuit is activated, and the precharge circuit is deactivated by the control signal line when the local write amplifier circuit is activated.

Abstract: A content addressable memory which detects whether p (where p is an integer of 2 or more) bit sequences coincide respectively with reference bit sequences, said content addressable memory comprising: q comparison units which compares bit groups obtained by dividing the p bit sequences into q (where q is an integer of 2 or more) parts with corresponding bit groups in the reference bit sequences in p times; a precharge unit which precharges output lines of said q comparison units; and a comparison control unit responsive to a decision of noncoincidence in at least one of said q comparison units while said q comparison units are conducting an rth (where r is an integer variable that is 1 or more and that is at most p?1, and p is an integer of 2 or more) comparison operation, which stops precharging to be performed by said precharge unit at time of an (r+1)th comparison operation and subsequent comparison operations.

Abstract: A semiconductor memory has word lines, bit lines, memory cells configured to store signals by transition states of transistors and configured to provide the bit lines with the signals addressed by the word lines, a leak detecting line, leak generators configured to provide the leak detecting line with a leakage current and a signal compensator configured to detect a voltage state of the leak detecting line and to change the signals transmitted by the bit lines.

Abstract: A content addressable memory which detects whether p (where p is an integer of 2 or more) bit sequences coincide respectively with reference bit sequences, said content addressable memory comprising: q comparison units which compares bit groups obtained by dividing the p bit sequences into q (where q is an integer of 2 or more) parts with corresponding bit groups in the reference bit sequences in p times; a precharge unit which precharges output lines of said q comparison units; and a comparison control unit responsive to a decision of noncoincidence in at least one of said q comparison units while said q comparison units are conducting an rth (where r is an integer variable that is 1 or more and that is at most p−1, and p is an integer of 2 or more) comparison operation, which stops precharging to be performed by said precharge unit at time of an (r+1)th comparison operation and subsequent comparison operations.

Abstract: A semiconductor memory has word lines, bit lines, memory cells configured to store signals by transition states of transistors and configured to provide the bit lines with the signals addressed by the word lines, a leak detecting line, leak generators configured to provide the leak detecting line with a leakage current and a signal compensator configured to detect a voltage state of the leak detecting line and to change the signals transmitted by the bit lines.

Abstract: A semiconductor memory comprising: a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction; a memory cell array constituted by the sub-memory cell arrays arranged in the first and a second direction; a plurality of local bit lines in the sub-memory arrays; a plurality of word lines in the sub-memory arrays; a plurality of global bit lines connected the local bit lines via switching circuits; a plurality of read/write circuits connected to the global bit lines; a selecting circuit selecting a first read/write circuits on the basis of a first address signal from a first bus and selecting a second read/write circuits on the basis of a second address signal from a second bus; a sub-memory cell array selecting circuit connected to the switching circuits, decoding the first and second address signals, and selecting a first sub-memory cell array, and a second sub-memory cell array; and an address decoding circuit decoding the first and second ad

Abstract: A memory operating method includes selecting memory cells on a word line; transmitting potential levels of memory cells selected by the word line; pre-charging bit lines; amplifying the potential levels of the memory cells selected by the word line which are read to the bit lines; pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal; driving the bus line on the basis of a gate control signal; and transmitting the gate control signal so as not to drive the bus line when an enable signal is in an inactive state, and transmitting the gate control signal so as to drive the bus line on the basis of the potential of the bus line and output data of the amplifying means when the enable signal is in an active state.

Abstract: A semiconductor device comprises a first bit line, a second bit line, a memory cell electrically coupled to the first bit line and the second bit line, a first amplification circuit configured to amplify a potential of the first bit line and a second amplification circuit configured to amplify a potential of the second bit line.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell array divided into a plurality of sub-arrays in each of which a specified number of storage elements are arranged in the row direction, a first bit line provided for each of the plurality of sub-arrays and connected to one of a pair of storage nodes complementary to each other in the specified number of storage elements, a second bit line to which the first bit line provided for each of the plurality of sub-arrays is commonly connected via switching means, a third bit line commonly connected to the other one of a pair of storage nodes complementary to each other in the specified number of storage elements in the plurality of sub-arrays, and a write circuit connected to the second bit line and the third bit line.

Abstract: A bus driving circuit comprises: a bus pre-charge part for pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal; a tristate buffer for driving the bus line on the basis of a gate control signal; and a gate control circuit for transmitting the gate control signal to the tristate buffer so as not to drive the bus line when an enable signal is in an inactive state, and for transmitting the gate control signal to the tristate buffer so as to drive the but line on the basis of the potential of the bus line and data inputted from a pre-charge type circuit when the enable signal is in an active state. Thus, it is possible to inhibit the influence of the coupling noises between bus lines, and it is possible to rapidly transfer data.

Abstract: A bus driving circuit comprises: a bus pre-charge part for pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal; a tristate buffer for driving the bus line on the basis of a gate control signal; and a gate control circuit for transmitting the gate control signal to the tristate buffer so as not to drive the bus line when an enable signal is in an inactive state, and for transmitting the gate control signal to the tristate buffer so as to drive the but line on the basis of the potential of the bus line and data inputted from a pre-charge type circuit when the enable signal is in an active state. Thus, it is possible to inhibit the influence of the coupling noises between bus lines, and it is possible to rapidly transfer data.

Abstract: A bus driving circuit comprises: a bus pre-charge part for pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal; a tristate buffer for driving the bus line on the basis of a gate control signal; and a gate control circuit for transmitting the gate control signal to the tristate buffer so as not to drive the bus line when an enable signal is in an inactive state, and for transmitting the gate control signal to the tristate buffer so as to drive the but line on the basis of the potential of the bus line and data inputted from a pre-charge type circuit when the enable signal is in an active state. Thus, it is possible to inhibit the influence of the coupling noises between bus lines, and it is possible to rapidly transfer data.

Abstract: A bus driving circuit comprises: a bus pre-charge part for pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal; a tristate buffer for driving the bus line on the basis of a gate control signal; and a gate control circuit for transmitting the gate control signal to the tristate buffer so as not to drive the bus line when an enable signal is in an inactive state, and for transmitting the gate control signal to the tristate buffer so as to drive the but line on the basis of the potential of the bus line and data inputted from a pre-charge type circuit when the enable signal is in an active state. Thus, it is possible to inhibit the influence of the coupling noises between bus lines, and it is possible to rapidly transfer data.

Abstract: A memory unit includes a plurality of memory cells arranged in the form of a matrix; word lines for selecting memory cells on the same line; bit lines for transmitting the potential levels of the memory cells selected by the word lines; a bit line pre-charge circuit for pre-charging the bit lines; a sense amplifier circuit for amplifying the potentials of the memory cells which are read to the bit lines; a bus pre-charge means for pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal; a tristate buffer for driving the bus line on the basis of a gate control signal; and a gate control circuit for transmitting the gate control signal to the tristate buffer so as not to drive the bus line when an enable signal is in an inactive state, and for transmitting the gate control signal to the tristate buffer so as to drive the bus line on the basis of the potential of the bus line and the output data of the sense amplifier circuit when the enable signal is in an active

Abstract: A semiconductor integrated circuit device comprises: a clock driver for outputting a clock signal; a clock wiring which is driven by the clock driver for transmitting the clock signal; a plurality of logic circuits which are connected to the clock wiring to be synchronously operated in response to the clock signal; and a plurality of delay circuits, each of which is provided between a corresponding one of the logic circuits and the clock wiring for delaying the clock signal, wherein a delay amount of each of the delay circuits is designed so that the delay amounts of the clock signal from the output of the clock driver to the inputs of the logic circuits are equal to each other. Thus, it is possible to reduce clock skew and to evade an increase in layout area.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell array divided into a plurality of sub-arrays in each of which a specified number of storage elements are arranged in the row direction, a first bit line provided for each of the plurality of sub-arrays and connected to one of a pair of storage nodes complementary to each other in the specified number of storage elements, a second bit line to which the first bit line provided for each of the plurality of sub-arrays is commonly connected via switching means, a third bit line commonly connected to the other one of a pair of storage nodes complementary to each other in the specified number of storage elements in the plurality of sub-arrays, and a write circuit connected to the second bit line and the third bit line.

Abstract: A semiconductor memory comprising: a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction; a memory cell array constituted by the sub-memory cell arrays arranged in the first and a second direction; a plurality of local bit lines in the sub-memory arrays; a plurality of word lines in the sub-memory arrays; a plurality of global bit lines connected the local bit lines via switching circuits; a plurality of read/write circuits connected to the global bit lines; a selecting circuit selecting a first read/write circuits on the basis of a first address signal from a first bus and selecting a second read/write circuits on the basis of a second address signal from a second bus; a sub-memory cell array selecting circuit connected to the switching circuits, decoding the first and second address signals, and selecting a first sub-memory cell array, and a second sub-memory cell array; and an address decoding circuit decoding the first and second ad

Abstract: A semiconductor device comprises a first bit line, a second bit line, a memory cell electrically coupled to the first bit line and the second bit line, a first amplification circuit configured to amplify a potential of the first bit line and a second amplification circuit configured to amplify a potential of the second bit line.

Abstract: A bus driving circuit comprises: a bus pre-charge part for pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal; a tristate buffer for driving the bus line on the basis of a gate control signal; and a gate control circuit for transmitting the gate control signal to the tristate buffer so as not to drive the bus line when an enable signal is in an inactive state, and for transmitting the gate control signal to the tristate buffer so as to drive the but line on the basis of the potential of the bus line and data inputted from a pre-charge type circuit when the enable signal is in an active state. Thus, it is possible to inhibit the influence of the coupling noises between bus lines, and it is possible to rapidly transfer data.