Abstract: A bus driving circuit comprises: a bus pre-charge part for pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal; a tristate buffer for driving the bus line on the basis of a gate control signal; and a gate control circuit for transmitting the gate control signal to the tristate buffer so as not to drive the bus line when an enable signal is in an inactive state, and for transmitting the gate control signal to the tristate buffer so as to drive the but line on the basis of the potential of the bus line and data inputted from a pre-charge type circuit when the enable signal is in an active state. Thus, it is possible to inhibit the influence of the coupling noises between bus lines, and it is possible to rapidly transfer data.

Abstract: When a fault cell is found in an initial state at the time of power-on, LRU bit is rewritten so that the LRU bit does not take an entry corresponding to a fault cell as an object of updating and then a LRU write inhibit flag is set to inhibit a write in the fault cell. If a fault cell is found during operation, a valid bit corresponding to an entry corresponding to the fault cell is rewritten to invalid condition. Then the LRU bit is rewritten so that the LRU bit does not take an entry corresponding to the fault cell as an object of updating and then a LRU write inhibit flag is set to inhibit a write in the fault cell.

Abstract: A decoding circuit decodes address signals of 7-bit so as to select one of 128 decoded signals preliminarily set to selective condition and keeps its selective condition. Then the decoding circuit switches the other decoded signals except the selected decoded signal from the selective condition to non-selective condition. A buffer circuit detects that the decoded signals different from the decoded signal kept in the selective condition have been switches from the selective condition to the non-selective condition by receiving the 128 decoded signals from the decoding circuit. Then the buffer circuit selects an output selective signal corresponding to the decoded signal in the selective condition, out of the 128 output selective signals corresponding to the 128 decoded signals, and makes the output selective signal in the selective condition.

Abstract: Erroneous operation protection circuits (EOPs) are provided between a plurality of precharge type data bus wirings which are set to predetermined potential beforehand and to which a plurality of circuit blocks are connected to transfer signals. Accordingly, an increase in stray capacitance of the data bus wirings can be suppressed to the lowest minimum to thus prevent erroneous operation due to coupling noises between the data bus wirings. The EOP comprises a coupling noise detector (CND) for detecting whether or not data transition on a first data bus wiring is caused by coupling noises due to capacitance between the first data bus wiring and a second data bus wiring being aligned in close vicinity to the first data bus wiring, and a precharge device for shifting potential of the first data bus wiring to return to predetermined potential if the coupling noise detector has detected the coupling noises.

Abstract: A semiconductor integrated circuit apparatus comprises a semiconductor substrate, a first well region formed in the upper surface of the semiconductor substrate, a first circuit formed in the first well region, first bias voltage supply functions for supplying a bias voltage to the first well region, a second well region formed in the upper surface of the semiconductor substrate such that it does not contact the first well region, a second circuit formed in the second well region, and second bias voltage supply functions for supplying a bias voltage to the second well region.

Abstract: A memory unit has, for each bit line, a latch circuit for holding data read out of a memory cell until the next access takes place, and a comparator for comparing data to be written into the memory cell and the data held in the latch circuit. If read and write operations consecutively occur at the same address and if some data bits to be written agree with corresponding data bits held in the latch circuits, there is no need of writing data for these bits. Accordingly, the write operation is disabled for these bits and is enabled only for bits that show disagreement between the data to be written and the data stored in the latch circuits. The power consumption of memory cells in a write operation is far greater than that in a read operation. Accordingly, omitting unnecessary write operations in the manner mentioned above greatly reduces the power consumption of the memory unit and the power consumption of a microprocessor that employs the memory unit.

Abstract: A phase-synchronizing type clock signal generating circuit including a DLL (delay line loop) circuit, capable of performing a similar operation for a DLL circuit even under the low-speed operation as in the high-speed operation. The clock signal generating circuit includes: a delay circuit for delaying an internal clock signal upon receipt of a reference clock signal externally provided; a selector circuit which selects and outputs either the reference clock signal or an output from the delay circuit, in accordance with a selector signal externally provided; a buffer circuit which delays the internal clock signal for as long as a signal passing delay time duration for the selector circuit; and a delay line loop which delays the reference clock signal upon receipt of an output signal from the selector circuit and that from the buffer circuit.

Abstract: A clock signal generating circuit is capable of testing a delay line loop (DLL) circuit by a method wherein, when an LSI circuit operates at a lower speed for a burn-in test, etc., the DLL circuit performs the same operation as when the LSI circuit operates normally at a high speed. This invention includes a selector for selecting either a reference clock signal or a test clock signal having a different phase with respect to the reference clock signal, and a delay line loop system phase-locked loop circuit for giving a delay to an output signal of the selector so as to get rid of a phase difference between the reference clock signal and an internal clock signal that has been propagated through a circuit to be supplied with a clock, and for generating the clock signal to be supplied to the circuit.

Abstract: A clock signal generation circuit performs a stable operation with respect to both a high frequency input clock signal and a sufficient low frequency testing clock signal.

Abstract: An arithmetic unit includes an arithmetic and logic circuit having n bits and capable of controlling the execution of either addition or subtraction by responding to a signal indicative of a positive or negative sign of a result of one preceding calculation, a register of n bits for temporarily storing data delivered out of the arithmetic and logic circuit, a register of n bits for delivering a divisor to the arithmetic and logic circuit, a shift register of n stages for sequentially storing signals indicative of a positive or negative sign of results of calculation by the arithmetic and logic circuit, and a shifter for shifting data of the register by one bit to the left and inserting data of the most significant bit of the shift register into the least significant bit to provide an output which in turn is delivered to the arithmetic and logic circuit. A conventional shifter having a bit length of 2n can be replaced with the shifter having a bit length of n and the shift register having a bit length of n.

Abstract: There is disclosed a data input/output control circuit comprising: an input/output circuit for carrying out input of data from the exterior or output of data thereto; and an output circuit such that when the input/output circuit carries out output of data, it delivers, to the input/output circuit, data generated in the exterior and transferred by way of a signal line, while when the input/output circuit carries out input of data, it allows the node between the input/output circuit and the signal line to be placed in high impedance state. In this control circuit, the output circuit includes a switching element and a discharge element connected in series between the signal line and the input/output circuit. The switching element is operative in such a manner that when the input/output circuit carries out output of data, it is closed, while when the input/output circuit carries out input of data, it is opened.