Patents by Inventor Yukihiro Sato
Yukihiro Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9698125Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.Type: GrantFiled: September 24, 2015Date of Patent: July 4, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yukihiro Sato, Katsuhiko Funatsu, Takamitsu Kanazawa, Masahiro Koido, Hiroyoshi Taya
-
Patent number: 9666518Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.Type: GrantFiled: January 31, 2017Date of Patent: May 30, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsuhiko Funatsu, Yukihiro Sato, Takamitsu Kanazawa, Masahiro Koido, Hiroyoshi Taya
-
Publication number: 20170141086Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.Type: ApplicationFiled: January 31, 2017Publication date: May 18, 2017Inventors: Katsuhiko FUNATSU, Yukihiro SATO, Takamitsu KANAZAWA, Masahiro KOIDO, Hiroyoshi TAYA
-
Patent number: 9641102Abstract: For example, a semiconductor device has a lead connected to a second portion of a chip mounting part on which a semiconductor chip to be a heat source is mounted and a lead connected to a third portion of the chip mounting part on which the semiconductor chip to be the heat source is mounted. Further, each of the leads has a protruding portion protruding from a sealing member. In this manner, it is possible to enhance a heat dissipation characteristic of the semiconductor device.Type: GrantFiled: November 16, 2015Date of Patent: May 2, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuhiro Mitamura, Koji Bando, Yukihiro Sato, Takamitsu Kanazawa
-
Publication number: 20170103940Abstract: On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Inventors: Akira MUTO, Koji BANDO, Yukihiro SATO, Kazuhiro MITAMURA
-
Patent number: 9576885Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.Type: GrantFiled: September 24, 2015Date of Patent: February 21, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsuhiko Funatsu, Yukihiro Sato, Takamitsu Kanazawa, Masahiro Koido, Hiroyoshi Taya
-
Publication number: 20170033035Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.Type: ApplicationFiled: June 6, 2016Publication date: February 2, 2017Inventors: Yukihiro SATO, Akira MUTO, Ryo KANDA, Takamitsu KANAZAWA
-
Patent number: 9530723Abstract: On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.Type: GrantFiled: September 22, 2015Date of Patent: December 27, 2016Assignee: Renesas Electronics CorporationInventors: Akira Muto, Koji Bando, Yukihiro Sato, Kazuhiro Mitamura
-
Patent number: 9508559Abstract: A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.Type: GrantFiled: September 18, 2013Date of Patent: November 29, 2016Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shoko Saito, Tomoyuki Okada, Kanji Takeuchi, Mitsufumi Naoe, Masahiko Minemura, Yukihiro Sato, Yoshito Konno, Yasuhiko Inada, Tomoaki Inaoka, Naoya Sashida
-
Patent number: 9478483Abstract: The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.Type: GrantFiled: February 11, 2013Date of Patent: October 25, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yukihiro Sato, Tomoaki Uno
-
Publication number: 20160233204Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the leadframe, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).Type: ApplicationFiled: April 19, 2016Publication date: August 11, 2016Inventors: Katsuhiko FUNATSU, Tomoaki UNO, Toru UEGURI, Yukihiro SATO
-
Patent number: 9396971Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.Type: GrantFiled: July 21, 2015Date of Patent: July 19, 2016Assignee: Renesas Electronics CorporationInventors: Yukihiro Sato, Nobuya Koike
-
Publication number: 20160163615Abstract: For example, a semiconductor device has a lead connected to a second portion of a chip mounting part on which a semiconductor chip to be a heat source is mounted and a lead connected to a third portion of the chip mounting part on which the semiconductor chip to be the heat source is mounted. Further, each of the leads has a protruding portion protruding from a sealing member. In this manner, it is possible to enhance a heat dissipation characteristic of the semiconductor device.Type: ApplicationFiled: November 16, 2015Publication date: June 9, 2016Inventors: Kazuhiro MITAMURA, Koji BANDO, Yukihiro SATO, Takamitsu KANAZAWA
-
Patent number: 9362238Abstract: A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.Type: GrantFiled: October 21, 2015Date of Patent: June 7, 2016Assignee: Renesas Electronics CorporationInventors: Katsuhiko Funatsu, Yukihiro Sato, Yuichi Yato, Tomoaki Uno
-
Publication number: 20160148859Abstract: On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.Type: ApplicationFiled: September 22, 2015Publication date: May 26, 2016Inventors: Akira MUTO, Koji BANDO, Yukihiro SATO, Kazuhiro MITAMURA
-
Patent number: 9343451Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).Type: GrantFiled: April 13, 2015Date of Patent: May 17, 2016Assignee: Renesas Electronics CorporationInventors: Katsuhiko Funatsu, Tomoaki Uno, Toru Ueguri, Yukihiro Sato
-
Publication number: 20160093589Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.Type: ApplicationFiled: September 24, 2015Publication date: March 31, 2016Inventors: Yukihiro SATO, Katsuhiko FUNATSU, Takamitsu KANAZAWA, Masahiro KOIDO, Hiroyoshi TAYA
-
Publication number: 20160089474Abstract: Provided is a collagen sponge which has compressive strength (stress) equivalent to that of a tissue into which the collagen sponge is to be implanted, has no unevenness in structure and stress, and has a pore structure for allowing cells to infiltrate thereinto. The collagen sponge is obtained by subjecting a collagen dispersion, a collagen solution, or a mixture thereof having a collagen concentration of 50 mg/ml or more to freeze-drying and insolubilization treatment thereafter. The collagen sponge thus obtained has a stress of from 10 kPa to 30 kPa when loaded with 10% strain, has in its surface and inside a pore structure having a mean pore diameter ranging from 50 ?m to 400 ?m, and has a pore diameter standard deviation equal to or less than 80% of the mean pore diameter.Type: ApplicationFiled: February 14, 2014Publication date: March 31, 2016Inventors: Ken NAKATA, Yukihiro SATO, Daisuke IKEDA, Ichiro FUJIMOTO
-
Publication number: 20160093594Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.Type: ApplicationFiled: September 24, 2015Publication date: March 31, 2016Inventors: Katsuhiko FUNATSU, Yukihiro SATO, Takamitsu KANAZAWA, Masahiro KOIDO, Hiroyoshi TAYA
-
Publication number: 20160043042Abstract: A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.Type: ApplicationFiled: October 21, 2015Publication date: February 11, 2016Inventors: Katsuhiko FUNATSU, Yukihiro SATO, Yuichi YATO, Tomoaki UNO