Patents by Inventor Yukihiro Sato
Yukihiro Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130082334Abstract: A semiconductor device is improved in reliability. A switching power MOSFET and a sense MOSFET for sensing a current flowing in the power MOSFET, which is smaller in area than the power MOSFET, are formed in one semiconductor chip. The semiconductor chip is mounted over a chip mounting portion via a conductive bonding material, and sealed in a resin. Over the main surface of the semiconductor chip, a metal plate is bonded to a source pad electrode of the power MOSFET. In the plan view, the metal plate does not overlap a sense MOSFET region where the sense MOSFET is formed. The metal plate is bonded to the source pad electrode so as to surround three of the sides of the sense MOSFET region.Type: ApplicationFiled: September 12, 2012Publication date: April 4, 2013Inventors: Hiroyuki NAKAMURA, Yukihiro Sato, Atsushi Fujiki, Tatsuhiro Seki
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Patent number: 8409007Abstract: In a game system, a server apparatus (3) that communicates with a plurality of game devices (1) stores play data elements for a plurality of players and public IDs for identifying a plurality of players in a latest play data table (T1) and a public ID table (T2). The server apparatus (3) transmits to a mobile terminal (4), which is being used by a player, information depending on latest play data elements stored in the latest play data table (T1), the latest play data elements belonging to other players who have been registered with the personal relationship table (T3) as a friend of the player possessing the mobile terminal (4). Upon receiving a public-ID-change request from a mobile terminal (4), which is being used by a player, the server apparatus (3) changes the public ID of the player stored in the public ID table (T2).Type: GrantFiled: August 31, 2006Date of Patent: April 2, 2013Assignee: Konami Digital Entertainment Co., Ltd.Inventors: Kenji Kobayashi, Yukizumi Terao, Yukihiro Sato, Masaru Nakamura
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Patent number: 8395364Abstract: The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.Type: GrantFiled: September 15, 2011Date of Patent: March 12, 2013Assignee: Renesas Electronics CorporationInventors: Yukihiro Sato, Tomoaki Uno
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Patent number: 8367479Abstract: To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.Type: GrantFiled: March 5, 2010Date of Patent: February 5, 2013Assignee: Renesas Electronics CorporationInventors: Hiroyuki Nakamura, Akira Muto, Nobuya Koike, Atsushi Nishikizawa, Yukihiro Sato, Katsuhiko Funatsu
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Patent number: 8351597Abstract: The present invention relates to an electronic device that can output received voice and input transmitted voice at the same time and enhances a suppression function for echo due to the received voice sneaking into the transmitted voice. An electronic device (e.g., portable telephone terminal device) outputs the received voice from a voice output unit (speaker), inputs the transmitted voice through a voice input unit (microphone), and includes an echo canceller unit that subtracts a pseudo echo signal for the received voice from the transmitted voice to suppress an echo component in the transmitted voice and a controlling unit that changes an echo suppression amount of the echo canceller unit in accordance with the received voice volume.Type: GrantFiled: September 25, 2007Date of Patent: January 8, 2013Assignee: Fujitsu LimitedInventors: Yukihiro Sato, Nobuhiro Mochizuki
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Publication number: 20120273892Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.Type: ApplicationFiled: July 11, 2012Publication date: November 1, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tomoaki UNO, Nobuyoshi MATSUURA, Yukihiro SATO, Keiichi OKAWA, Tetsuya KAWASHIMA, Kisho ASHIDA
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Patent number: 8299600Abstract: A semiconductor device is provided with improved reliability. A semiconductor chip is mounted over a chip mounting portion of a lead frame via solder. A metal plate is arranged over a source pad of the semiconductor chip and a lead portion of a lead frame via solder. A solder reflow process is performed thereby to bond the semiconductor chip over the chip mounting portion with a solder, and to bond the metal plate to the source pad and the lead portion with the other solders. The lead frame is formed of a copper alloy, and thus has its softening temperature higher than the temperature of the solder reflow process. The metal plate is formed of oxygen-free copper, and has its softening temperature lower than the temperature of the solder reflow process, whereby the metal plate is softened in the solder reflow process. Thereafter, a gate pad electrode of the semiconductor chip is coupled to a lead portion via the wire, a sealing resin portion is formed, and then the lead frame is cut.Type: GrantFiled: November 16, 2009Date of Patent: October 30, 2012Assignee: Renesas Electronics CorporationInventors: Yukihiro Sato, Katsuhiko Funatsu, Hiroyuki Nakamura
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Patent number: 8299599Abstract: To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP1, power MOSFETs Q1 and Q2 for the switch, a diode DD1 for detecting the heat generation of the power MOSFET Q1, a diode DD2 for detecting the heat generation of the power MOSFET Q2, and plural pad electrodes PD are formed. The power MOSFET Q1 and the diode DD1 are arranged in a first MOSFET region RG1 on the side of a side SD1, and the power MOSFET Q2 and the diode DD2 are arranged in a second MOSFET region RG2 on the side of a side SD2. The diode DD1 is arranged along the side SD1, the diode DD2 is arranged along the side SD2, and all pad electrodes PD other than the pad electrodes PDS1 and PDS2 for the source are arranged along a side SD3 between the diodes DD1 and DD2.Type: GrantFiled: March 3, 2011Date of Patent: October 30, 2012Assignee: Renesas Electronics CorporationInventors: Hiroyuki Nakamura, Atsushi Fujiki, Tatsuhiro Seki, Nobuya Koike, Yukihiro Sato, Kisho Ashida
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Publication number: 20120261825Abstract: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.Type: ApplicationFiled: June 26, 2012Publication date: October 18, 2012Inventors: Nobuya KOIKE, Atsushi Fujiki, Norio Kido, Yukihiro Sato, Hiroyuki Nakamura
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Publication number: 20120242713Abstract: An electronic device includes a driver configured to drive light emitting elements under matrix control; a first electric current path to connect a first light emitting element to the driver, the first electric current path including parallel signal lines to connect a cathode of the first light emitting element to two or more terminals of the driver; a second electric current path to connect a second light emitting element to the driver, at least a portion of the second electric current path extending from a cathode of the second light emitting element sharing a common path with the first electric current path; and a backflow prevention element provided on the first electric current path and inserted between the cathode of the first light emitting element and the common path.Type: ApplicationFiled: March 9, 2012Publication date: September 27, 2012Applicant: FUJITSU LIMITEDInventors: Nozomi YAGI, Yukihiro Sato
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Patent number: 8237232Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.Type: GrantFiled: March 17, 2011Date of Patent: August 7, 2012Assignee: Renesas Electronics CorporationInventors: Tomoaki Uno, Nobuyoshi Matsuura, Yukihiro Sato, Keiichi Okawa, Tetsuya Kawashima, Kisho Ashida
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Patent number: 8232629Abstract: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.Type: GrantFiled: August 20, 2007Date of Patent: July 31, 2012Assignee: Renesas Electronics CorporationInventors: Nobuya Koike, Atsushi Fujiki, Norio Kido, Yukihiro Sato, Hiroyuki Nakamura
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Patent number: 8113957Abstract: A game system allowing a player corresponding to a terminal, from which communication has been cut, to restart the game from the game situation at the moment of communication cut. The server has a game continuation device for continuing the game except the error terminal in a case where the error terminal occurs, and a server restart device for transmitting situation information of each player after communication recovery as information for restart, and restarting the game by communication with only the error terminal. The error terminal comprises a terminal restart device for restarting the game after communication recovery based on the situation information included in the information for restart, and a virtual input operation device for functioning as a virtual player instead of players P corresponding to other terminal.Type: GrantFiled: November 8, 2006Date of Patent: February 14, 2012Assignee: Konami Digital Entertainment Co., Ltd.Inventors: Yukihiro Sato, Katsutoshi Yoshida, Masato Miyazaki
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Publication number: 20120001342Abstract: The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.Type: ApplicationFiled: September 15, 2011Publication date: January 5, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yukihiro SATO, Tomoaki UNO
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Patent number: 8040708Abstract: The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.Type: GrantFiled: June 8, 2009Date of Patent: October 18, 2011Assignee: Renesas Electronics CorporationInventors: Yukihiro Sato, Tomoaki Uno
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Publication number: 20110221616Abstract: An electronic apparatus includes a detection circuit having at least a first contact point, a second contact point and a third contact point; an input key unit changes states of the individual contact points based on an accepted input operation, and a detection-circuit control unit obtains a detection signal corresponding to changed states of the individual contact points from the detection circuit, and detects the input operation from the obtained detection signal.Type: ApplicationFiled: March 3, 2011Publication date: September 15, 2011Applicant: FUJITSU LIMITEDInventors: Hitoshi YAMASAKI, Yukihiro SATO, Kazumasa SUGAWARA
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Publication number: 20110215400Abstract: To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP1, power MOSFETs Q1 and Q2 for the switch, a diode DD1 for detecting the heat generation of the power MOSFET Q1, a diode DD2 for detecting the heat generation of the power MOSFET Q2, and plural pad electrodes PD are formed. The power MOSFET Q1 and the diode DD1 are arranged in a first MOSFET region RG1 on the side of a side SD1, and the power MOSFET Q2 and the diode DD2 are arranged in a second MOSFET region RG2 on the side of a side SD2. The diode DD1 is arranged along the side SD1, the diode DD2 is arranged along the side SD2, and all pad electrodes PD other than the pad electrodes PDS1 and PDS2 for the source are arranged along a side SD3 between the diodes DD1 and DD2.Type: ApplicationFiled: March 3, 2011Publication date: September 8, 2011Inventors: Hiroyuki NAKAMURA, Atsushi FUJIKI, Tatsuhiro SEKI, Nobuya KOIKE, Yukihiro SATO, Kisho ASHIDA
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Publication number: 20110169102Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.Type: ApplicationFiled: March 17, 2011Publication date: July 14, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tomoaki Uno, Nobuyoshi Matsuura, Yukihiro Sato, Keiichi Okawa, Tetsuya Kawashima, Kisho Ashida
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Patent number: 7969000Abstract: A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the pMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.Type: GrantFiled: February 16, 2010Date of Patent: June 28, 2011Assignee: Renesas Electronics CorporationInventors: Yukihiro Sato, Norio Kido, Tatsuhiro Seki, Katsuo Ishizaka, Ichio Shimizu
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Patent number: 7932588Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.Type: GrantFiled: January 28, 2010Date of Patent: April 26, 2011Assignee: Renesas Electronics CorporationInventors: Tomoaki Uno, Nobuyoshi Matsuura, Yukihiro Sato, Keiichi Okawa, Tetsuya Kawashima, Kisho Ashida