Abstract: Provided is a platinum complex having a structure represented by formula (I): wherein A1 to A3 each independently represent a 5-membered or 6-membered unsaturated ring, A3 is optionally formed between A1 and A2; X1, X2, and X3 each independently represent carbon or nitrogen; R1 represents hydrogen, substituted or unsubstituted C1-C6 alkyl, —CF2H, —CFH2, substituted or unsubstituted C6-C12 aryl or —CmF2m+1, m is an integer of 1 to 5; R2 and R3 each independently represent hydrogen, C1-C12 alkyl, substituted or unsubstituted C1-C6 alkoxyl, substituted or unsubstituted C6-C12 aryl, or —CnF2n+1, n is an integer of 0 to 3; p and q each independently represent an integer of 1 to 2; and when p or q is equal to 2, two R2's or R3's may join to form a C3-C8 aromatic or nitrogen-containing heteroaromatic ring.

Abstract: An atomic layer deposition equipment and an atomic layer deposition process method are disclosed. The atomic layer deposition equipment includes a chamber, a substrate stage, at least one bottom pumping port, at least one hollow component, a baffle and a shower head assembly, wherein the hollow component has an exhaust hole. The baffle is below the hollow component and forms an upper exhaust path with the hollow component, so that the flow field of the precursor in the atomic layer deposition process can be adjusted to a slow flow field to make a uniform deposition on the substrate.

Abstract: A fin height monitoring structure including a substrate, isolation structures, a first word line, and a second word line is provided. The substrate includes a first region and a second region. The isolation structures are located in the substrate of the first region to define at least one active area. The substrate in the active area has a fin that is higher than the isolation structures. The first word line is located on the isolation structures of the first region and on the fin of the first region. The second word line is located on the substrate of the second region.

Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

Abstract: Provided is a platinum complex having a structure represented by formula (I): wherein A1 to A3 each independently represent a 5-membered or 6-membered unsaturated ring, A3 is optionally formed between A1 and A2; X1, X2, and X3 each independently represent carbon or nitrogen; R1 represents hydrogen, substituted or unsubstituted C1-C6 alkyl, —CF2H, —CFH2, substituted or unsubstituted C6-C12 aryl or —CmF2m+1, m is an integer of 1 to 5; R2 and R3 each independently represent hydrogen, C1-C12 alkyl, substituted or unsubstituted C1-C6 alkoxyl, substituted or unsubstituted C6-C12 aryl, or —CnF2n+1, n is an integer of 0 to 3; p and q each independently represent an integer of 1 to 2; and when p or q is equal to 2, two R2's or R3's may join to form a C3-C8 aromatic or nitrogen-containing heteroaromatic ring.

Abstract: An iridium complex has the structure: wherein X? and X? independently represent carbon or nitrogen; X1, X2, X3, and X4 independently represent carbon or nitrogen; R1 and R5 independently represent substituted or unsubstituted C1-C12 alkyl; R2, R3, and R4 independently represent hydrogen, C1-C12 alkyl, substituted or unsubstituted C6-C12 aryl, or —CmF2m+1, m is from 1 to 3; each of m and n is from 1 to 3; A1 and A2 independently represent an unsaturated 5-membered or 6-membered ring; B is —O—, —NR— or —CR2—, A2 may join with —NR— or —CR2— to form a C9-C14 N-heteroaromatic or aromatic ring; b is 0 or 1; R6 is hydrogen, fluorine, substituted or unsubstituted C1-C12 alkyl, substituted or unsubstituted C1-C6 alkoxyl, substituted or unsubstituted C6-C12 aryl, substituted or unsubstituted C1-C6 amino, or —CxF2x+1, x is from 1 to 3; and p is from 1 to 3.

Abstract: An atomic layer deposition equipment and an atomic layer deposition process method are disclosed. The atomic layer deposition equipment includes a chamber, a substrate stage, at least one bottom pumping port, at least one hollow component, a baffle and a shower head assembly, wherein the hollow component has an exhaust hole. The baffle is below the hollow component and forms an upper exhaust path with the hollow component, so that the flow field of the precursor in the atomic layer deposition process can be adjusted to a slow flow field to make a uniform deposition on the substrate.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: A dynamic balancing apparatus includes a dynamic balancing assembly and a plurality of damping particles. The dynamic balancing assembly includes at least two structural members separately arranged on a rotating shaft connected to a rotor, wherein each structural member includes at least one recess portion. The plurality of damping particles are introduced into at least one recess portion of each structural member, such that a centroid of each structural member deviates from the axis. Accordingly, each structural member generates inertial force and moment of inertia as rotation of the rotor to offset another inertial force and moment of inertia generated by centroid deviation of the rotor while rotating to achieve dynamic balance. The plurality of damping particles can move in the recess portion as rotation of the rotor to induce friction and collision so as to achieve the effects of vibration reduction and noise reduction.

Abstract: A dynamic balancing apparatus includes a dynamic balancing assembly and a plurality of damping particles. The dynamic balancing assembly includes at least two structural members separately arranged on a rotating shaft connected to a rotor, wherein each structural member includes at least one recess portion. The plurality of damping particles are introduced into at least one recess portion of each structural member, such that a centroid of each structural member deviates from the axis. Accordingly, each structural member generates inertial force and moment of inertia as rotation of the rotor to offset another inertial force and moment of inertia generated by centroid deviation of the rotor while rotating to achieve dynamic balance. The plurality of damping particles can move in the recess portion as rotation of the rotor to induce friction and collision so as to achieve the effects of vibration reduction and noise reduction.

Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: A memory device includes a semiconductor substrate, a logic transistor, and a storage transistor. The semiconductor substrate has a logic region and a memory region. The logic transistor is disposed on the logic region, in which the logic transistor comprises a high-k metal gate structure. The storage transistor is disposed on the memory region, in which the storage transistor includes a charge storage structure and a high-k metal gate structure. The charge storage structure is disposed on the memory region. The high-k metal gate structure is disposed on the charge storage structure.

Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

Abstract: A fin height monitoring structure including a substrate, isolation structures, a first word line, and a second word line is provided. The substrate includes a first region and a second region. The isolation structures are located in the substrate of the first region to define at least one active area. The substrate in the active area has a fin that is higher than the isolation structures. The first word line is located on the isolation structures of the first region and on the fin of the first region. The second word line is located on the substrate of the second region.

Abstract: A method for forming a semiconductor is provided. The method includes etching a trench in a semiconductor substrate, in which the trench surrounds a device region of the semiconductor substrate; forming a conductive feature in the trench; and forming a transistor on the device region of the semiconductor substrate after forming the conductive feature.

Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.