Abstract: A processing path generating device including an intuitive path teaching device and a controller is provided. The intuitive path teaching device is provided for gripping and moving with respect to a workpiece to create a moving path. The intuitive path teaching device has a detecting portion for detecting a surface feature of the workpiece. The controller is connected to the intuitive path teaching device. The controller generates a processing path according to the moving path of the intuitive path teaching device and the surface feature of the workpiece.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: Technology is disclosed for transferring money anonymously between a sender and a recipient by use of a token. In some embodiments, the disclosed technology involves communication between a mobile payment application (“App”) and a payment service system (PSS). Upon the recipient's request, the App, installed on the recipient's device, generates the token, and provides the token to both the recipient and the PSS. The PSS receives both the token and the recipient's identification information from the App, associates the token with the identification information, and stores such association. The recipient, on the other hand, transfers the token to the sender, who forwards it to the PSS to request a money transfer. The PSS receives the token and identifies the recipient's identification information based on the previously stored association with the token. With the identification information, the PSS determines the recipient's financial account to execute the money transfer.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

Abstract: A platinum complex, an OLED and an apparatus for providing visible emission or near-infrared (NIR) emission using the same are described. The platinum complex has a structure represented by formula (I): wherein A1 to A4 each independently represent a 5-membered or 6-membered unsaturated ring, a first chelating ligand including A1 and A4 fragments has a minus one formal charge, and a second chelating ligand including A2 and A3 fragments has a minus one formal charge.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: Disclosed herein is a hinge antibody capable of being selectively activated in a target cell or tissue to treat a condition therein. The hinge antibody includes a functional antibody, two inhibitory domains and four cleavable linkers. The functional antibody is capable of treating the condition in an activated state, and has two light chains and two heavy chains. Each inhibitory domain includes a hinge domain of an immunoglobulin and consists of two peptide arms. Each cleavable linker includes a peptide substrate cleavable by an enzyme specifically or highly expressed in the target cell or tissue, and connects one of the peptide arms of the inhibitory domains to the N-terminal of one of the light chains and heavy chains of the functional antibody. Also disclosed herein are methods for preparing and using this hinge antibody.

Abstract: A memory device includes a semiconductor substrate, a logic transistor, and a storage transistor. The semiconductor substrate has a logic region and a memory region. The logic transistor is disposed on the logic region, in which the logic transistor comprises a high-k metal gate structure. The storage transistor is disposed on the memory region, in which the storage transistor includes a charge storage structure and a high-k metal gate structure. The charge storage structure is disposed on the memory region. The high-k metal gate structure is disposed on the charge storage structure.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.