Patents by Inventor Yun Wu

Yun Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162051
    Abstract: Some implementations described herein include systems and techniques for fabricating a stacked die product. The systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. One type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. Properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.
    Type: Application
    Filed: April 27, 2023
    Publication date: May 16, 2024
    Inventors: Kuo-Ming WU, Hau-Yi HSIAO, Kai-Yun YANG, Che Wei YANG, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
  • Publication number: 20240148301
    Abstract: The present invention provides a smart wearable device, which is held on an upper body of a wearer by a plurality of contact pad sets, and has a connection unit, a first sensing module, a second sensing module, and an extension unit.
    Type: Application
    Filed: November 7, 2022
    Publication date: May 9, 2024
    Inventors: Chien-Hsiang Chang, Yang-Cheng Lin, Wei-Chih Lien, Tseng-Ping Chiu, Pei-Yun Wu, Bo Liu
  • Publication number: 20240153558
    Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Chun-Yun Wu, Chen-Ming Hung
  • Patent number: 11978714
    Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
  • Patent number: 11978664
    Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu
  • Publication number: 20240145884
    Abstract: A battery connection structure includes a plurality of battery units connected in series. At least one battery unit is connected in series to other battery units through a temperature switch; the temperature switch includes a first connection member connected to a first electrode terminal of the battery unit and a second connection member connected to a second electrode terminal of the battery unit; at normal operating temperature, the first connection member and the second connection member are disconnected, and the first connection member and the second connection member are respectively connected to the two electrode terminals of the battery unit; when the temperature is higher than the normal operating temperature, the first connection member and/or the second connection member are/is deformed and disconnected from the corresponding electrode terminal(s) of the battery unit, and the first connection member and the second connection member are connected.
    Type: Application
    Filed: March 2, 2021
    Publication date: May 2, 2024
    Applicants: MICROVAST POWER SYSTEMS CO., LTD., MICROVAST, INC.
    Inventors: Yang WU, Ningqiang XIAO, Yun ZHAO, Wenjuan Liu MATTIS
  • Publication number: 20240133473
    Abstract: The application relates to an anti-back-transfer intake structure of a rotating detonation combustion chamber including a Tesla valve communicating with the rotating detonation combustion chamber and arranged at an inlet of the rotating detonation combustion chamber. The Tesla valve includes a casing and a flow passage, the casing is coaxially connected with an outer wall of the rotating detonation combustion chamber, the flow passage is arranged in the casing, and the flow passage has an inlet end for introducing air, and an outlet end connected with an annular passage of the rotating detonation combustion chamber.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 25, 2024
    Inventors: Feilong SONG, Yun WU, Xin CHEN, Min JIA, Huimin SONG, Shanguang GUO, Zhao YANG, Jiaojiao WANG
  • Publication number: 20240136291
    Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.
    Type: Application
    Filed: January 12, 2023
    Publication date: April 25, 2024
    Inventors: Hsiang-Ku SHEN, Chen-Chiu HUANG, Chia-Nan LIN, Man-Yun WU, Wen-Tzu CHEN, Sean YANG, Dian-Hao CHEN, Chi-Hao CHANG, Ching-Wei LIN, Wen-Ling CHANG
  • Patent number: 11967546
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20240129363
    Abstract: A distributed task offloading and computing resources management method based on energy harvesting is provided, including: establishing a task local computing model and an edge cloud computing model; establishing a device maximum benefit objective function based on the perturbation Lyapunov optimization algorithm and a mobile edge computing server maximum benefit objective function; pre-selecting, by the device based on a pre-screening criteria, a mobile edge computing server for task offloading; calculating an optimal task size strategy for performing task offloading by the device to the selected mobile edge computing server by using a Lagrange multiplier algorithm and a KKT condition; obtaining an optimal quotation strategy of the mobile edge computing server for the device in each of time slots; and obtaining a solution of the optimal task size strategy meeting a Stackelberg equilibrium and a solution of the optimal dynamic quotation strategy meeting the Stackelberg equilibrium as a resource allocation str
    Type: Application
    Filed: November 4, 2021
    Publication date: April 18, 2024
    Applicant: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Yun LI, Zhixiu YAO, Shichao XIA, Guangfu WU
  • Patent number: 11961886
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and nanostructures suspended over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure also includes a contact vertically over the source/drain structure and a first conductive structure vertically over the gate structure. The semiconductor structure also includes a second conductive structure in contact with a top surface of the first conductive structure and a top surface of the contact and including an extending portion laterally sandwiched between the first conductive structure and the contact.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Heng Wang, Pang-Chi Wu, Chao-Hsun Wang, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11958935
    Abstract: A polyurethane insulation foam composition is disclosed herein. The polyurethane insulation foam comprises: (i) an aromatic isocyanate compound; (ii) an isocyanate reactive compound; (iii) water; (iv) a tertiary amine compound; (v) a hydrophilic carboxylic acid compound; (vi) a halogenated olefin compound; (vii) a stabilizing compound, and (vii) optionally, other additives.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: April 16, 2024
    Inventors: Yangjun Cai, Lifeng Wu, Sachchida Singh, Yun-Shan Liu
  • Patent number: 11956307
    Abstract: A distributed task offloading and computing resources management method based on energy harvesting is provided, including: establishing a task local computing model and an edge cloud computing model; establishing a device maximum benefit objective function based on the perturbation Lyapunov optimization algorithm and a mobile edge computing server maximum benefit objective function; pre-selecting, by the device based on a pre-screening criteria, a mobile edge computing server for task offloading; calculating an optimal task size strategy for performing task offloading by the device to the selected mobile edge computing server by using a Lagrange multiplier algorithm and a KKT condition; obtaining an optimal quotation strategy of the mobile edge computing server for the device in each of time slots; and obtaining a solution of the optimal task size strategy meeting a Stackelberg equilibrium and a solution of the optimal dynamic quotation strategy meeting the Stackelberg equilibrium as a resource allocation str
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: April 9, 2024
    Assignee: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Yun Li, Zhixiu Yao, Shichao Xia, Guangfu Wu
  • Publication number: 20240113234
    Abstract: An integrated chip including a gate layer. An insulator layer is over the gate layer. A channel structure is over the insulator layer. A pair of source/drains are over the channel structure and laterally spaced apart by a dielectric layer. The channel structure includes a first channel layer between the insulator layer and the pair of source/drains, a second channel layer between the insulator layer and the dielectric layer, and a third channel layer between the second channel layer and the dielectric layer. The first channel layer, the second channel layer, and the third channel layer include different semiconductors.
    Type: Application
    Filed: January 4, 2023
    Publication date: April 4, 2024
    Inventors: Ya-Yun Cheng, Wen-Ling Lu, Yu-Chien Chiu, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11949234
    Abstract: A method for making a spatio-temporal combined optimal scheduling strategy of a mobile energy storage (MES) system includes: inputting data of a power system, a traffic system, and an MES system; setting a time interval, and initializing a time interval counter; inputting real-time fault, traffic, and MES data; and performing rolling optimization and solving, and delivering regulation decision instructions of the MES system, till a fault is removed. The core of the present disclosure is to propose a spatio-temporal combined optimal model of the MES system to describe spatio-temporal coupling statuses of an energy storage vehicle, a traffic network, and a power distribution network. The present disclosure provides guidance for an optimal scheduling decision of the MES system by properly regulating a traveling path and charging and discharging power of the MES system, thereby supporting high-reliability operation of the power distribution network.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: April 2, 2024
    Assignees: Electric Power Science & Research Institute of State Grid Tianjin Electric Power Company, State Grid Tianjin Electric Power Company, State Grid Corporation of China
    Inventors: Shiqian Ma, Bin Wu, Yun Liu, Xianxu Huo, Yi Ding, Lei Wu, Tianhao Wang
  • Publication number: 20240103220
    Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Kuo-Chiang Ting, Sung-Hui Huang, Shang-Yun Hou, Chi-Hsi Wu
  • Publication number: 20240103915
    Abstract: A task offloading and resource allocation method in an uncertain network environment is provided. A task offloading process is modeled as a two-stage offloading model. The model is optimized to a task offloading and resource allocation problem based on two-stage stochastic programming. Based on a stochastic simulation algorithm, the task offloading and resource allocation problem is transformed to a sample mean approximation problem. The sample mean approximation problem is decoupled to a local computing resource allocation sub-problem, a transmission power and edge computing resource joint allocation sub-problem, and an offloading decision sub-problem. The three sub-problems are solved respectively by using a standard Lagrange multiplier algorithm, by using a genetic algorithm, and by analyzing delay estimation and energy consumption budget of local computing and delay estimation and energy consumption budget of edge computing.
    Type: Application
    Filed: November 4, 2021
    Publication date: March 28, 2024
    Applicant: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Yun LI, Zhixiu YAO, Shichao XIA, Guangfu WU, Hongcheng ZHUANG
  • Patent number: 11941821
    Abstract: An image sleep analysis method and system thereof are disclosed. During sleep duration, a plurality of visible-light images of a body are obtained. Positions of image differences are determined by comparing the visible-light images. A plurality of features of the visible-light images are identified and positions of the features are determined. According to the positions of the image differences and features, the motion intensities of the features are determined. Therefore, a variation of the motion intensities is analyzed and recorded to provide accurate sleep quality.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: March 26, 2024
    Assignee: YUN YUN AI BABY CAMERA CO., LTD.
    Inventors: Bo-Zong Wu, Meng-Ta Chiang, Chia-Yu Chen, Shih-Yun Shen
  • Patent number: 11938222
    Abstract: The present application relates to a pregabalin sustained release composition, comprising: (a) an active ingredient; (b) a matrix-forming agent; (c) a swelling agent; (d) a gelling agent; and optionally a filler. The pregabalin sustained release composition provided in the present application can rapidly swell in volume when exposed to aqueous medium until exceeding the dimeter of human gastric pyloric (13 mm). It thereby prolongs the gastric emptying time to increase the retention time of pregabalin in the stomach and enhances absorption of pregabalin in the small intestine and ascending colon. Moreover, the pregabalin sustained release composition provided herein achieves a sustained release for 24 h, which allows QD (once a day) administration, reduces administration number, and improves patient compliance.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: March 26, 2024
    Assignee: BEIJING TIDE PHARMACEUTICAL CO., LTD.
    Inventors: Zhaolu Zhu, Yun Wu, Di Lu, Yanping Zhao, Liying Zhou, Yanan Liu
  • Patent number: D1024460
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: April 23, 2024
    Assignee: PLANDDO CO., LTD.
    Inventors: Tsung-Te Sun, Chao-Shun Liang, Chia-Hsin Wu, Ping-Yun Su, Yu-Huai Yang