Abstract: An integrated chip including a gate layer. An insulator layer is over the gate layer. A channel structure is over the insulator layer. A pair of source/drains are over the channel structure and laterally spaced apart by a dielectric layer. The channel structure includes a first channel layer between the insulator layer and the pair of source/drains, a second channel layer between the insulator layer and the dielectric layer, and a third channel layer between the second channel layer and the dielectric layer. The first channel layer, the second channel layer, and the third channel layer include different semiconductors.

Abstract: A method for making a spatio-temporal combined optimal scheduling strategy of a mobile energy storage (MES) system includes: inputting data of a power system, a traffic system, and an MES system; setting a time interval, and initializing a time interval counter; inputting real-time fault, traffic, and MES data; and performing rolling optimization and solving, and delivering regulation decision instructions of the MES system, till a fault is removed. The core of the present disclosure is to propose a spatio-temporal combined optimal model of the MES system to describe spatio-temporal coupling statuses of an energy storage vehicle, a traffic network, and a power distribution network. The present disclosure provides guidance for an optimal scheduling decision of the MES system by properly regulating a traveling path and charging and discharging power of the MES system, thereby supporting high-reliability operation of the power distribution network.

Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

Abstract: A task offloading and resource allocation method in an uncertain network environment is provided. A task offloading process is modeled as a two-stage offloading model. The model is optimized to a task offloading and resource allocation problem based on two-stage stochastic programming. Based on a stochastic simulation algorithm, the task offloading and resource allocation problem is transformed to a sample mean approximation problem. The sample mean approximation problem is decoupled to a local computing resource allocation sub-problem, a transmission power and edge computing resource joint allocation sub-problem, and an offloading decision sub-problem. The three sub-problems are solved respectively by using a standard Lagrange multiplier algorithm, by using a genetic algorithm, and by analyzing delay estimation and energy consumption budget of local computing and delay estimation and energy consumption budget of edge computing.

Abstract: An image sleep analysis method and system thereof are disclosed. During sleep duration, a plurality of visible-light images of a body are obtained. Positions of image differences are determined by comparing the visible-light images. A plurality of features of the visible-light images are identified and positions of the features are determined. According to the positions of the image differences and features, the motion intensities of the features are determined. Therefore, a variation of the motion intensities is analyzed and recorded to provide accurate sleep quality.

Abstract: The present application relates to a pregabalin sustained release composition, comprising: (a) an active ingredient; (b) a matrix-forming agent; (c) a swelling agent; (d) a gelling agent; and optionally a filler. The pregabalin sustained release composition provided in the present application can rapidly swell in volume when exposed to aqueous medium until exceeding the dimeter of human gastric pyloric (13 mm). It thereby prolongs the gastric emptying time to increase the retention time of pregabalin in the stomach and enhances absorption of pregabalin in the small intestine and ascending colon. Moreover, the pregabalin sustained release composition provided herein achieves a sustained release for 24 h, which allows QD (once a day) administration, reduces administration number, and improves patient compliance.

Abstract: A manufacturing method of an electronic element module is provided. The method includes: disposing a plurality of first micro-light-emitting diodes on a first temporary substrate; and replacing at least one defective micro-light-emitting diode of the first micro-light-emitting diodes with at least one second micro-light-emitting diode. The first micro-light-emitting diodes and at least one second micro-light-emitting diode are distributed on the first temporary substrate. The first micro-light-emitting diodes and at least one second micro-light-emitting diode have same properties, and at least one of the appearance difference, the height difference and the orientation difference exists between the first micro-light-emitting diodes and at least one second micro-light-emitting diode. A semiconductor structure and a display panel are also provided.

Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.

Abstract: Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.

Abstract: Information output methods and apparatuses, computer equipment and readable storage media which relate to the field of computer technology are provided. The information output method includes: detecting whether a search connection is established between a delivery terminal and a beacon device deployed by a target physical object by using a pre-cached joint beacon atlas bound to the target physical object, where the joint beacon atlas records a set of communication identifiers covered by a physical object; if the search connection is established between the delivery terminal and the beacon device deployed by the target physical object, outputting a corresponding time point when the search connection is in a stable state as information of a delivery resource arriving at the target physical object.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly and a first driving assembly. The movable assembly is movable relative to the fixed assembly. The first driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The optical element driving mechanism further includes a first opening, and an external light beam travels along a first axis to pass through the first opening.

Abstract: In some examples, an apparatus may include a backlight unit (BLU) including an electronic integrated circuit layer, a photonic integrated circuit layer, a color conversion module, and a display interface layer. In some examples, a BLU may include at least one laser or may be configured to receive laser light from at least one external laser source. Laser light may be transmitted towards a portion of the display interface layer using the photonic integrated circuit. Color conversion modules may be used to convert the laser light into one or more desired colors. Example apparatus may be used in head-mounted devices such as augmented reality and/or virtual reality devices. Other devices, methods, systems, and computer-readable media are also disclosed.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an interconnect structure over a substrate. The method includes forming a first conductive pad and a mask layer over the interconnect structure. The mask layer covers a top surface of the first conductive pad. The method includes forming a metal oxide layer over a sidewall of the first conductive pad. The method includes forming a second conductive pad over the first conductive pad and passing through the mask layer. The first conductive pad and the second conductive pad are made of different materials.

Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: A gateway device selection method is provided. The method includes: receiving, by a terminal device, a message from a gateway device, where the message includes identification information of the gateway device, and the identification information of the gateway device indicates information about the gateway device; determining, by the terminal device, that the identification information of the gateway device is consistent with preset identification information of a gateway device on the terminal device, and using the gateway device as a selected gateway device; and sending, by the terminal device, a data packet to the selected gateway device. This helps the terminal device correctly identify the gateway device to which the terminal device is to send data.

Abstract: A thermoplastic vulcanizate is provided. The thermoplastic vulcanizate includes: (A) about 100 parts by weight of a styrene copolymer rubber; (B) about 40-90 parts by weight of a thermoplastic elastomer; (C) about 5-15 parts by weight of an interfacial compatible resin; and (D) about 0.2-3 parts by weight of a cross-linking formulation, wherein the content of component (A) is greater than the content of component (B). Component (A) is dispersed in component (B) in the form of particles with a particle size of about 0.5-10 ?m.

Abstract: A semiconductor device and method of fabricating the same include a substrate, a first epitaxial layer, a first protection layer, and a contact etching stop layer. The substrate includes a PMOS transistor region, and the first epitaxial layer is disposed on the substrate, within the PMOS transistor region. The first protection layer is disposed on the first epitaxial layer, covering surfaces of the first epitaxial layer. The contact etching stop layer is disposed on the first protection layer and the substrate, wherein a portion of the first protection layer is exposed from the contact etching stop layer.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.