Patents by Inventor Yung-Chin Hou
Yung-Chin Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8671382Abstract: A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.Type: GrantFiled: April 8, 2013Date of Patent: March 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng, Yung-Chin Hou
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Patent number: 8671367Abstract: Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files.Type: GrantFiled: December 19, 2008Date of Patent: March 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hsing Wang, Lee-Chung Lu, Yung-Chin Hou, Lie-Szu Juang
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Patent number: 8631366Abstract: Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.Type: GrantFiled: February 18, 2010Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Lee-Chung Lu, Li-Chun Tien, Yi-Kan Cheng, Chun-Hui Tai, Ta-Pen Guo, Yuan-Te Hou
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Patent number: 8507957Abstract: A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer.Type: GrantFiled: May 2, 2011Date of Patent: August 13, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Shyue-Shyh Lin, Li-Chun Tien, Shu-Min Chen, Pin-Dai Sue
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Patent number: 8504972Abstract: An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region.Type: GrantFiled: February 1, 2010Date of Patent: August 6, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, David Barry Scott, Lee-Chung Lu, Li-Chun Tien
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Patent number: 8504965Abstract: A method of designing integrated circuits includes providing a design of an integrated circuit at a first scale, wherein the integrated circuit includes a shrinkable circuit including a first intellectual property (IP); and a non-shrinkable circuit including a second IP having a hierarchical structure. A marker layer is formed to cover the non-shrinkable circuit, wherein the shrinkable circuit is not covered by the marker layer. The electrical performance of the non-shrinkable circuit is simulated using a simulation tool, wherein the simulated non-shrinkable circuit is at a second scale smaller than the first scale.Type: GrantFiled: September 30, 2010Date of Patent: August 6, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Liu, Chung-Hsing Wang, Yung-Chin Hou, Lie-Szu Juang
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Patent number: 8431985Abstract: A device includes a semiconductor substrate including an active region, a gate electrode directly over the active region, and a gate contact plug over and electrically coupled to the gate electrode. The gate contact plug includes at least a portion directly over, and vertically overlapping, the active region.Type: GrantFiled: August 6, 2010Date of Patent: April 30, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Lee-Chung Lu, Shyue-Shyh Lin, Li-Chun Tien
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Patent number: 8418112Abstract: A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.Type: GrantFiled: March 3, 2011Date of Patent: April 9, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng, Yung-Chin Hou
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Publication number: 20120280287Abstract: A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer.Type: ApplicationFiled: May 2, 2011Publication date: November 8, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Shyue-Shyh Lin, Li-Chun Tien, Shu-Min Chen, Pin-Dai Sue
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Publication number: 20120226479Abstract: A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.Type: ApplicationFiled: March 3, 2011Publication date: September 6, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng, Yung-Chin Hou
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Patent number: 8261219Abstract: A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.Type: GrantFiled: June 4, 2008Date of Patent: September 4, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kun-Lung Chen, Shine Chien Chung, Yung-Chin Hou, Yu-Chun Wu
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Patent number: 8255837Abstract: A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.Type: GrantFiled: November 12, 2009Date of Patent: August 28, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Yi-Kan Cheng, Yuan-Te Hou, Yung-Chin Hou, Li-Chun Tien
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Patent number: 8217469Abstract: The present disclosure provides a device in an integrated circuit. The device includes an active region in a semiconductor substrate; an isolation region adjacent the active region; a gate disposed on the active region and extending to the isolation region in a first direction; and a gate contact disposed within the isolation region, having a portion directly overlying and contacting the gate, and having a geometry horizontally extending to a first dimension in the first direction and a second dimension in a second direction approximately perpendicular to the first direction. The first dimension is greater than the second dimension.Type: GrantFiled: February 8, 2010Date of Patent: July 10, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Yuh-Jier Mii, Kuo-Tung Sung, Li-Chun Tien
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Patent number: 8201111Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.Type: GrantFiled: August 2, 2011Date of Patent: June 12, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin, Hsiao-Shu Chao, Ping-Heng Yeh, Min-Hong Wu, Yao-Ching Ku, Tsong-Hua Ou
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Publication number: 20120084745Abstract: A method of designing integrated circuits includes providing a design of an integrated circuit at a first scale, wherein the integrated circuit includes a shrinkable circuit including a first intellectual property (IP); and a non-shrinkable circuit including a second IP having a hierarchical structure. A marker layer is formed to cover the non-shrinkable circuit, wherein the shrinkable circuit is not covered by the marker layer. The electrical performance of the non-shrinkable circuit is simulated using a simulation tool, wherein the simulated non-shrinkable circuit is at a second scale smaller than the first scale.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Liu, Chung-Hsing Wang, Yung-Chin Hou, Lie-Szu Juang
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Publication number: 20120032268Abstract: A device includes a semiconductor substrate including an active region, a gate electrode directly over the active region, and a gate contact plug over and electrically coupled to the gate electrode. The gate contact plug includes at least a portion directly over, and vertically overlapping, the active region.Type: ApplicationFiled: August 6, 2010Publication date: February 9, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Lee-Chung Lu, Shyue-Shyh Lin, Li-Chun Tien
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Publication number: 20110291200Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: ApplicationFiled: April 13, 2011Publication date: December 1, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ali KESHAVARZI, Ta-Pen GUO, Helen Shu-Hui CHANG, Hsiang-Jen TSENG, Shyue-Shyh LIN, Lee-Chung LU, Chung-Cheng WU, Li-Chun TIEN, Jung-Chan YANG, Shu-Min CHEN, Min CAO, Yung-Chin HOU
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Publication number: 20110289466Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.Type: ApplicationFiled: August 2, 2011Publication date: November 24, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin, Hsiao-Shu Chao, Ping-Heng Yeh, Min-Hong Wu, Yao-Ching Ku, Tsong-Hua Ou
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Patent number: 8001494Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.Type: GrantFiled: October 13, 2008Date of Patent: August 16, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin, Hsiao-Shu Chao, Ping-Heng Yeh, Min-Hong Wu, Yao-Ching Ku, Tsong-Hua Ou
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Publication number: 20110140203Abstract: The present disclosure provides a device in an integrated circuit. The device includes an active region in a semiconductor substrate; an isolation region adjacent the active region; a gate disposed on the active region and extending to the isolation region in a first direction; and a gate contact disposed within the isolation region, having a portion directly overlying and contacting the gate, and having a geometry horizontally extending to a first dimension in the first direction and a second dimension in a second direction approximately perpendicular to the first direction. The first dimension is greater than the second dimension.Type: ApplicationFiled: February 8, 2010Publication date: June 16, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Chin Hou, Yuh-Jier Mii, Kuo-Tung Sung, Li-Chun Tien