Patents by Inventor Yung-Chin Hou
Yung-Chin Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7932566Abstract: An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly pitch. A first boundary region has at least one isolation area that lies between the type-1 cells and the type-2 cell in the X-direction. The first boundary region includes at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the default poly pitch of the type-1 cells and a second portion that complies with the non-default poly pitch of the type-2 cell.Type: GrantFiled: December 31, 2008Date of Patent: April 26, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Li-Chun Tien, Lee-Chung Lu, Ping Chung Li, Ta-Pen Guo
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Patent number: 7913141Abstract: A system is disclosed for reducing current leakages in an integrated circuit (IC), the system comprises one or more separated power supply lines connecting between one or more power sources and an isolated circuitry, one or more switches on the separated power supply lines for controlling the connections between the power sources and the isolated circuitry, and one or more controllers for turning the switches on or off according to one or more predetermined conditions.Type: GrantFiled: August 16, 2006Date of Patent: March 22, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Lee-Chung Yu, Chung-Hsing Wang, Yung-Chin Hou
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Publication number: 20100281446Abstract: Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.Type: ApplicationFiled: February 18, 2010Publication date: November 4, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Lee-Chung Lu, Li-Chun Tien, Yi-Kan Cheng, Chun-Hui Tai, Ta-Pen Guo, Yuan-Te Hou
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Patent number: 7821039Abstract: An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.Type: GrantFiled: August 18, 2008Date of Patent: October 26, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Chun Tien, Lee-Chung Lu, Yung-Chin Hou, Chun-Hui Tai, Ta-Pen Guo, Sheng-Hsin Chen, Ping Chung Li
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Publication number: 20100269081Abstract: An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region.Type: ApplicationFiled: February 1, 2010Publication date: October 21, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, David Barry Scott, Lee-Chung Lu, Li-Chun Tien
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Patent number: 7808051Abstract: An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.Type: GrantFiled: December 29, 2008Date of Patent: October 5, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Lee-Chung Lu, Ta-Pen Guo, Li-Chun Tien, Ping Chung Li, Chun-Hui Tai, Shu-Min Chen
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Patent number: 7797668Abstract: A method for converting a circuit design into a semiconductor device includes the following steps. A first set of deign information is provided for representing the circuit design. Priority design information, which represents a priority portion of the circuit design, is extracted from the first set of design information. The priority design information is processed for generating a second set of design information. The semiconductor device is fabricated based on the first and second sets of design information. The second set of design information contains enhanced fabrication conditions as opposed to those of the first set of design information for optimizing the conversion of the circuit design into the semiconductor device.Type: GrantFiled: January 18, 2006Date of Patent: September 14, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gwan Sin Chang, Ru-Gun Liu, Chih-Ming Lai, Yung-Chin Hou
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Publication number: 20100196803Abstract: A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.Type: ApplicationFiled: November 12, 2009Publication date: August 5, 2010Inventors: Lee-Chung Lu, Yi-Kan Cheng, Yuan-Te Hou, Yung-Chin Hou, Li-Chun Tien
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Publication number: 20100164614Abstract: An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly pitch. A first boundary region has at least one isolation area that lies between the type-1 cells and the type-2 cell in the X-direction. The first boundary region includes at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the default poly pitch of the type-1 cells and a second portion that complies with the non-default poly pitch of the type-2 cell.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Yung-Chin Hou, Li-Chun Tien, Lee-Chung Lu, Ping Chung Li, Ta-Pen Guo
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Publication number: 20100127333Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes an active region in a semiconductor substrate; a first field effect transistor (FET) disposed in the active region; and an isolation structure disposed in the active region. The FET includes a first gate; a first source formed in the active region and disposed on a first region adjacent the first gate from a first side; and a first drain formed in the active region and disposed on a second region adjacent the first gate from a second side. The isolation structure includes an isolation gate disposed adjacent the first drain; and an isolation source formed in the active region and disposed adjacent the isolation gate such that the isolation source and the first drain are on different sides of the isolation gate.Type: ApplicationFiled: November 21, 2008Publication date: May 27, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Chin Hou, Ta-Pen Guo, Harry Chuang, Carlos H. Diaz, Lee-Chung Lu, Li-Chun Tien, Oscar M. K. Law, Chih-Chiang Chang, Chun-Hui Tai, Jonathan Lee
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Publication number: 20100095253Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.Type: ApplicationFiled: October 13, 2008Publication date: April 15, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Chin HOU, Ying-Chou CHENG, Ru-Gun LIU, Chih-Ming LAI, Yi-Kan CHENG, Chung-Kai LIN, Hsiao-Shu CHAO, Ping-Heng YEH, Min-Hong WU, Yao-Ching KU, Tsong-Hua OU
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Publication number: 20100078725Abstract: An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.Type: ApplicationFiled: December 29, 2008Publication date: April 1, 2010Inventors: Yung-Chin Hou, Lee-Chung Lu, Ta-Pen Guo, Li-Chun Tien, Ping Chung Li, Chun-Hui Tai, Shu-Min Chen
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Publication number: 20090326873Abstract: Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files.Type: ApplicationFiled: December 19, 2008Publication date: December 31, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Hsing Wang, Lee-Chung Lu, Yung-Chin Hou, Lie-Szu Juang
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Publication number: 20090315079Abstract: An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.Type: ApplicationFiled: August 18, 2008Publication date: December 24, 2009Inventors: Li-Chun Tien, Lee-Chung Lu, Yung-Chin Hou, Chun-Hui Tai, Ta-Pen Guo, Sheng-Hsin Chen, Ping Chung Li
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Patent number: 7467365Abstract: This invention discloses a method for sanity checking integrated circuit (IC) designs based on one or more predefined sub-circuits with at least one predefined checking criteria, the method comprising automatically reading one or more netlists, identifying one or more sub-circuits in the netlists isomorphic to at least one of predefined sub-circuits, identifying one or more device parameters for sanity checking the identified sub-circuits, and comparing the identified device parameters against the predefined checking criteria.Type: GrantFiled: September 14, 2006Date of Patent: December 16, 2008Assignee: Taiwan Semiconductor Manufacturing Co.Inventors: George H. Chang, Yi-Kan Cheng, Chen-Teng Fan, Chen-Lin Yang, Yung-Chin Hou, Chu-Ping James Wang
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Patent number: 7458051Abstract: A semiconductor structure including at least one spare cell is disclosed. The semiconductor structure includes a first conductive line coupled to a power supply, and a second conductive line coupled to a complementary power supply. At least one spare cell is decoupled from the first or second conductive line for being selectively connected to at least one normally functioning electronic components, the first conductive line and the second conductive line only during a rerouting process for reducing leakage power of the semiconductor structure.Type: GrantFiled: November 17, 2005Date of Patent: November 25, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Chin Hou, Lee-Chung Lu, Chu-Ping Wang, Li-Chun Tien
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Publication number: 20080235635Abstract: A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.Type: ApplicationFiled: June 4, 2008Publication date: September 25, 2008Inventors: Kun-Lung Chen, Shine Chien Chung, Yung-Chin Hou, Yu-Chun Wu
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Patent number: 7401302Abstract: A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.Type: GrantFiled: April 29, 2005Date of Patent: July 15, 2008Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Kun-Lung Chen, Shine Chien Chung, Yung-Chin Hou, Yu-Chun Wu
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Publication number: 20080082876Abstract: A system is disclosed for reducing current leakages in an integrated circuit (IC), the system comprises one or more separated power supply lines connecting between one or more power sources and an isolated circuitry, one or more switches on the separated power supply lines for controlling the connections between the power sources and the isolated circuitry, and one or more controllers for turning the switches on or off according to one or more predetermined conditions.Type: ApplicationFiled: August 16, 2006Publication date: April 3, 2008Inventors: Lee-Chung Yu, Chung-Hsing Wang, Yung-Chin Hou
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Patent number: 7350177Abstract: A configurable logic and memory block (CLMB) and a configurable logic device are disclosed. The CLMB includes one or more static random access memory (SRAM) cells, a first output module for generating a first output by reading at least one SRAM cell when the CLMB functions as an SRAM, a second output module for generating a second output by reading at least one SRAM cell when the CLMB functions as a program logic device (PLD), wherein data on one or more bitlines coupled to the SRAM cells are controllably feeding into the first and second output modules. The configurable logic device can provide various Boolean logic functions using pass gates.Type: GrantFiled: July 13, 2005Date of Patent: March 25, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shine Chien Chung, Yung-Chin Hou, Kun Lung Chen, Yu-Chun Wu