Abstract: An additive manufacturing model assembly includes: an additive manufacturing model formed by additive manufacturing in which laminated metal powder is melted; and a metal non-additive manufacturing model formed by a method different from the additive manufacturing, the additive manufacturing model assembly is configured by assembling the additive manufacturing model and the non-additive manufacturing model, the additive manufacturing model assembly has: a contact portion at which the additive manufacturing model and the non-additive manufacturing model are in contact with each other; and a fixing portion by which the additive manufacturing model and the non-additive manufacturing model are fixed to each other, the fixing portion being located at a same position as the contact portion or a position different from the contact portion, and a thickness of the additive manufacturing model is thinner than a thickness of the non-additive manufacturing model at the contact portion.

Abstract: A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.

Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.

Abstract: The present disclosure intends to facilitate tearing a metal sheath even in a case where the metal sheath is incorporated in an optical fiber cable. The optical fiber cable of the present disclosure includes a cable core arranged at a central portion and accommodating a plurality of optical fibers gathered together, an inner layer sheath arranged on an outer circumference of the cable core and sheathing the cable core, a metal sheath arranged on an outer circumference of the inner layer sheath and wound around the inner layer sheath, an outer layer sheath arranged on an outer circumference of the metal sheath and sheathing the metal sheath, and at least one outer sheath tearing string arranged in a longitudinal direction inside the metal sheath.

Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes first and second transistors and first and second capacitors. Each of the first and second transistors includes a gate insulator and a gate electrode over an oxide. Each of the first and second capacitors includes a conductor, a dielectric over the conductor, and the oxide. The first and second transistors are provided between the first capacitor and the second capacitor. One of a source and a drain of the first transistor is also used as one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is also used as one electrode of the first capacitor. The other of the source and the drain of the second transistor is also used as one electrode of the second capacitor. The channel lengths of the first and second transistors are larger than the lengths in a direction parallel to short sides of fourth and fifth conductors.

Abstract: the present invention provides a method for producing a protein having a supramolecular structure in which a bioactive substance is encapsulated, comprising: (I) bringing a subunit of a protein, which forms a supramolecular structure, a bioactive substance, and a solution for forming the protein having the supramolecular structure from the subunit into contact with one another in a flow micro mixer.

Abstract: A semiconductor device with a large storage capacity per unit area is provided. A semiconductor device includes a memory cell. The memory cell includes a first conductor; a first insulator over the first conductor; a first oxide over the first insulator and including a first region, a second region, and a third region positioned between the first region and the second region; a second insulator over the first oxide; a second conductor over the second insulator; a third insulator positioned in contact with a side surface of the first region; and a second oxide positioned on the side surface of the first region, with the third insulator therebetween. The first region includes a region overlapping the first conductor. The third region includes a region overlapped by the second conductor. The first region and the second region have a lower resistance than the third region.

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j?1th sub memory cell.

Abstract: A semiconductor device with high on-state current and high reliability is provided. The semiconductor device includes first to fifth insulators, first to third oxides, and first to fourth conductors; the fifth insulator includes an opening in which the second oxide is exposed; the third oxide is placed in contact with a bottom portion of the opening and a side portion of the opening; the second insulator is placed in contact with the third oxide; the third conductor is provided in contact with the second insulator; the third insulator is placed in contact with a top surface of the third conductor and the second insulator; and the fourth conductor is in contact with the third insulator and the top surface of the third conductor and placed in the opening.

Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first transistor, a second transistor, and an electrode. The first transistor and the second transistor include an oxide, a gate insulator over the oxide, and a gate. The electrode is connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor. The channel length of the first transistor is longer than the short side of the first conductor. The channel length of the second transistor is longer than the short side of the second conductor.

Abstract: To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j-lth sub memory cell.

Abstract: A semiconductor device with a large storage capacity per unit area is provided. A semiconductor device includes a memory cell. The memory cell includes a first conductor; a first insulator over the first conductor; a first oxide over the first insulator and including a first region, a second region, and a third region positioned between the first region and the second region; a second insulator over the first oxide; a second conductor over the second insulator; a third insulator positioned in contact with a side surface of the first region; and a second oxide positioned on the side surface of the first region, with the third insulator therebetween. The first region includes a region overlapping the first conductor. The third region includes a region overlapped by the second conductor. The first region and the second region have a lower resistance than the third region.

Abstract: A semiconductor device with high on-state current and high reliability is provided. The semiconductor device includes first to fifth insulators, first to third oxides, and first to fourth conductors; the fifth insulator includes an opening in which the second oxide is exposed; the third oxide is placed in contact with a bottom portion of the opening and a side portion of the opening; the second insulator is placed in contact with the third oxide; the third conductor is provided in contact with the second insulator; the third insulator is placed in contact with a top surface of the third conductor and the second insulator; and the fourth conductor is in contact with the third insulator and the top surface of the third conductor and placed in the opening.

Abstract: An integrated circuit for a power supply circuit that generates an output voltage from an input voltage. The power supply circuit includes a transformer, a transistor controlling an inductor current flowing through a primary coil of the transformer, a first capacitor, and a first diode charging the first capacitor. The integrated circuit is configured to control switching of the transistor. The integrated circuit includes a first terminal configured to receive a voltage across the first capacitor; a second terminal configured to receive a feedback voltage corresponding to the output voltage; a driving signal output circuit configured to output a driving signal to increase a switching period of the transistor, in response to a decrease in a load current; a driver circuit configured to drive the transistor in response to the driving signal; and a determination circuit configured to determine whether the power supply voltage drops below a first voltage.

Abstract: An integrated circuit for a power supply circuit. The integrated circuit includes an oscillator circuit configured to output an oscillator voltage that rises with a predetermined slope from a first voltage, upon an inductor current of the power supply circuit becoming smaller than a first predetermined value, an error voltage output circuit configured to output an error voltage corresponding to a difference between a reference voltage and a feedback voltage corresponding to the output voltage, a drive circuit configured to turn on and off a transistor of the power supply circuit respectively upon the inductor current becoming smaller than the first predetermined value, and upon the oscillator voltage reaching a second voltage that is based on the error voltage, and an output circuit configured to change the first and/or second voltage based on a rectified voltage obtained by full-wave rectification of the AC voltage, and to output the changed voltage.

Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.

Abstract: A semiconductor material is an oxide including a metal element and nitrogen, in which the metal element is indium (In), an element M (M is aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn)), and zinc (Zn) and nitrogen is taken into an oxygen vacancy or bonded to an atom of the metal element.

Abstract: A method for producing an objective protein by using animal cells as an expression host is provided. The objective protein is produced by culturing animal cells having an objective protein-producing ability in the presence of an L-cysteine derivative such as (2RS,4R)-2-methyl-2,4-thiazolidinedicarboxylic acid 2-ethyl ester.

Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.