Patents by Inventor Yuta Endo

Yuta Endo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10699904
    Abstract: A transistor that is formed using an oxide semiconductor film is provided. A transistor that is formed using an oxide semiconductor film with reduced oxygen vacancies is provided. A transistor having excellent electrical characteristics is provided. A semiconductor device includes a first insulating film, a first oxide semiconductor film, a gate insulating film, and a gate electrode. The first insulating film includes a first region and a second region. The first region is a region that transmits less oxygen than the second region does. The first oxide semiconductor film is provided at least over the second region.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 30, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Kosei Noda, Yuichi Sato
  • Publication number: 20200194590
    Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.
    Type: Application
    Filed: December 27, 2019
    Publication date: June 18, 2020
    Inventors: Shunpei YAMAZAKI, Yuta ENDO, Yoko TSUKAMOTO
  • Publication number: 20200144906
    Abstract: When an input voltage changes due to switching of an AC power supply, as a result of a change in a timing at which an inductor current becomes zero and an element voltage of a switching element becomes local minimum, a switching loss increases. Provided is a power supply controller that includes a switch control unit that controls an on/off of a switching element of a boost chopper; a detection unit that detects that a first value based on an inductor voltage of an inductor of the boost chopper is less than a threshold: and a delay adjustment unit that adjusts a delay time from when the detection unit detects that the first value is less than the threshold until when the switch control unit turns on the switching element according to a second value based on the inductor voltage.
    Type: Application
    Filed: October 24, 2019
    Publication date: May 7, 2020
    Inventor: Yuta ENDO
  • Publication number: 20200126991
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. A semiconductor device includes a memory cell. The memory cell includes a first conductor; a first insulator over the first conductor; a first oxide over the first insulator and including a first region, a second region, and a third region positioned between the first region and the second region; a second insulator over the first oxide; a second conductor over the second insulator; a third insulator positioned in contact with a side surface of the first region; and a second oxide positioned on the side surface of the first region, with the third insulator therebetween. The first region includes a region overlapping the first conductor. The third region includes a region overlapped by the second conductor. The first region and the second region have a lower resistance than the third region.
    Type: Application
    Filed: May 29, 2018
    Publication date: April 23, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hajime KIMURA, Takayuki IKEDA, Kiyoshi KATO, Yuta ENDO, Junpei SUGAO
  • Publication number: 20200119199
    Abstract: A semiconductor device having favorable characteristics is provided. In a semiconductor device including a transistor, the transistor includes a first oxide, a second oxide over the first oxide, an insulator over the second oxide, and a conductor over the insulator. The first oxide includes a channel formation region and a first region and a second region positioned so that the channel formation region is sandwiched therebetween. The second oxide is provided so as to be in contact with the channel formation region, part of the first region, and part of the second region. The first region and the second region have lower concentrations of oxygen than the channel formation region.
    Type: Application
    Filed: May 15, 2018
    Publication date: April 16, 2020
    Inventors: Shunpei YAMAZAKI, Naoki OKUNO, Yuta ENDO, Yuki IMOTO
  • Patent number: 10593683
    Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j-1th sub memory cell.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: March 17, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Shuhei Nagatsuka, Tamae Moriwaka, Yuta Endo
  • Patent number: 10546958
    Abstract: A miniaturized transistor with less variation and highly stable electrical characteristics is provided. Further, high performance and high reliability of a semiconductor device including the transistor are achieved. A semiconductor and a conductor are formed over a substrate, a sacrificial layer is formed over the conductor, and an insulator is formed to cover the sacrificial layer. After that, a top surface of the insulator is removed to expose a top surface of the sacrificial layer. The sacrificial layer and a region of the conductor overlapping with the sacrificial layer are removed, whereby a source region, a drain region, and an opening are formed. Next, a gate insulator and a gate electrode are formed in the opening.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yuta Endo
  • Publication number: 20200006567
    Abstract: A high-performance and highly reliable semiconductor device can be provided. The semiconductor device includes a first oxide; a second oxide over the first oxide; a source electrode and a drain electrode over the second oxide; a third oxide over the second oxide, the source electrode, and the drain electrode; a fourth oxide over the third oxide; a gate insulating film over the fourth oxide; and a gate electrode over the gate insulating film. The band gap of the first oxide is substantially the same as the band gap of the fourth oxide, the band gap of the second oxide is substantially the same as the band gap of the third oxide, the band gap of the first oxide is larger than the band gap of the second oxide, and the fourth oxide is less likely to transmit oxygen than the third oxide.
    Type: Application
    Filed: February 7, 2018
    Publication date: January 2, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuta ENDO, Hiromi SAWAI, Hajime KIMURA, Shunpei YAMAZAKI
  • Publication number: 20200006328
    Abstract: A favorable semiconductor device for miniaturization and high integration is provided. One embodiment of the present invention includes a first oxide including a first region and second region adjacent to each other, a third region and a fourth region with the first region and the second region provided therebetween, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, and a second conductor over the second region with the third insulator provided therebetween. A part of the third insulator is positioned between the second conductor and the side surface of the second insulator.
    Type: Application
    Filed: January 31, 2018
    Publication date: January 2, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Yuta ENDO, Shinya SASAGAWA, Shuhei NAGATSUKA
  • Publication number: 20200006402
    Abstract: A semiconductor device with high aperture ratio is provided. The semiconductor device includes a transistor and a capacitor having a pair of electrodes. An oxide semiconductor layer formed over the same insulating surface is used for a channel formation region of the transistor and one of the electrodes of the capacitor. The other electrode of the capacitor is a transparent conductive film. One electrode of the capacitor is electrically connected to a wiring formed over the insulating surface over which a source electrode or a drain electrode of the transistor is provided, and the other electrode of the capacitor is electrically connected to one of the source electrode and the drain electrode of the transistor.
    Type: Application
    Filed: September 10, 2019
    Publication date: January 2, 2020
    Inventor: Yuta ENDO
  • Patent number: 10522689
    Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Hitomi Sato, Kosei Noda, Yuta Endo, Mizuho Ikarashi, Keitaro Imai, Atsuo Isobe, Yutaka Okazaki
  • Patent number: 10522397
    Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Hideomi Suzawa, Sachiaki Tezuka, Tetsuhiro Tanaka, Toshiya Endo, Mitsuhiro Ichijo
  • Patent number: 10522691
    Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuta Endo, Yoko Tsukamoto
  • Publication number: 20190371798
    Abstract: A semiconductor device including a first oxide including a first region and a second region adjacent to each other and a third region and a fourth region with the first region and the second region sandwiched between the third region and the fourth region, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, a second conductor over the second region with the third insulator positioned between the second region and the second conductor and on the side surface of the second insulator with the third insulator positioned between the side surface of the second insulator and the second conductor, and a fourth insulator covering the first oxide, the second oxide, the first insulator, the first conductor, the second insulator, the third insulator, and th
    Type: Application
    Filed: February 6, 2018
    Publication date: December 5, 2019
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Yuta ENDO, Shuhei NAGATSUKA
  • Patent number: 10461101
    Abstract: A semiconductor device with high aperture ratio is provided. The semiconductor device includes a transistor and a capacitor having a pair of electrodes. An oxide semiconductor layer formed over the same insulating surface is used for a channel formation region of the transistor and one of the electrodes of the capacitor. The other electrode of the capacitor is a transparent conductive film. One electrode of the capacitor is electrically connected to a wiring formed over the insulating surface over which a source electrode or a drain electrode of the transistor is provided, and the other electrode of the capacitor is electrically connected to one of the source electrode and the drain electrode of the transistor.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: October 29, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yuta Endo
  • Publication number: 20190312149
    Abstract: A high-performance and highly reliable semiconductor device is provided. The semiconductor device includes: a first oxide; a source electrode; a drain electrode; a second oxide over the first oxide, the source electrode, and the drain electrode; a gate insulating film over the second oxide; and a gate electrode over the gate insulating film. The source electrode is electrically connected to the first oxide. The drain electrode is electrically connected to the first oxide. Each of the first oxide and the second oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. Each of the first oxide and the second oxide includes more In atoms than element M atoms. An atomic ratio of the In, the Zn, and the element M in the first oxide is equal to or similar to an atomic ratio of the In, the Zn, and the element M in the second oxide.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Inventors: Yuta ENDO, Hiromi SAWAI, Hajime KIMURA
  • Patent number: 10403646
    Abstract: A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a first insulating layer; a first oxide layer over the first insulating layer; a semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer over the semiconductor layer; a second insulating layer over the first insulating layer; a third insulating layer over the second insulating layer, the source electrode layer, and the drain electrode layer; a second oxide layer over the semiconductor layer; a gate insulating layer over the second oxide layer; a gate electrode layer over the gate insulating layer; and a fourth insulating layer over the third insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: September 3, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yuta Endo, Kazuya Hanaoka
  • Patent number: 10388796
    Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a first conductor over a substrate; a first insulator over the first conductor; an oxide over the first insulator; a second insulator over the oxide; a second conductor over the second insulator; a third insulator over the second conductor; a fourth insulator in contact with a side surface of the second insulator, a side surface of the second conductor, and a side surface of the third insulator; and a fifth insulator in contact with the oxide, the first insulator, and the fourth insulator. The first insulator and the fifth insulator are in contact with each other in a region on the periphery of the side of the oxide. The oxide includes a first region where a channel is formed; a second region adjacent to the first region; a third region adjacent to the second region; and a fourth region adjacent to the third region.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuta Endo, Yoshiaki Oikawa
  • Patent number: 10374098
    Abstract: A high-performance and highly reliable semiconductor device is provided. The semiconductor device includes: a first oxide; a source electrode; a drain electrode; a second oxide over the first oxide, the source electrode, and the drain electrode; a gate insulating film over the second oxide; and a gate electrode over the gate insulating film. The source electrode is electrically connected to the first oxide. The drain electrode is electrically connected to the first oxide. Each of the first oxide and the second oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. Each of the first oxide and the second oxide includes more In atoms than element M atoms. An atomic ratio of the In, the Zn, and the element M in the first oxide is equal to or similar to an atomic ratio of the In, the Zn, and the element M in the second oxide.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Hiromi Sawai, Hajime Kimura
  • Publication number: 20190237586
    Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.
    Type: Application
    Filed: March 15, 2019
    Publication date: August 1, 2019
    Inventors: Yuta ENDO, Hideomi SUZAWA, Sachiaki TEZUKA, Tetsuhiro TANAKA, Toshiya ENDO, Mitsuhiro ICHIJO