Abstract: A non-transitory computer-readable recording medium stores therein a simulation program that causes a computer to execute a process including acquiring coordinates of particles disposed in a virtual space, moving, in a first coordinate axis direction among coordinate axes that define the coordinates on the virtual space, a window with a width of a cutoff radius used for cutoff of calculation of an interaction between two particles, determining whether first particles that enter the window by the moving and second particles that exist in the window are within the cutoff radius and, when the first particles and the second particles exist, generating a particle pair, and iterating the moving of the window and the generating of the particle pair.

Abstract: An arithmetic processing apparatus includes a processor. The processor is configured to execute a parallel calculation on a plurality of pieces of floating-point data; determine whether or not information loss is to occur in the parallel calculation; and output a result of the parallel calculation when it is determined that the information loss is not to occur, and execute a sequential calculation on the plurality of pieces of floating-point data to output the result of the sequential calculation when it is determined that the information loss is to occur.

Abstract: A computer-implemented method of an arithmetic processing, the method including: identifying maximum absolute values of individual dimensions by projecting a maximum absolute value in a direction of each of the individual dimensions of a tensor represented by a multidimensional array, the tensor in which a value is set for each of elements of the array; identifying a minimum value that indicates a minimum maximum absolute value among the maximum absolute values of the individual dimensions; and setting a quantization range for the tensor on a basis of the minimum value.

Abstract: A non-transitory computer-readable storage medium storing a random number generation program that causes a processor included in a computer to execute a process, the process includes generating a second seed list that includes a new seed for each new random number sequence based on a first seed list that includes a seed for each random number sequence regarding a plurality of the random number sequences with a predetermined length, generating a random number with a predetermined length for each new random number sequence based on a seed included in the second seed list, determining whether or not the generated random number with the predetermined length matches the seed included in the second seed list, and repeatedly generating the second seed list until the random number with the predetermined length does not match the seed included in the second seed list.

Abstract: A random number generating circuit includes M random number generators, where M is an integer greater than or equal to 2, configured to be independent of each other and generate M random number sequences, a delay adjustment circuit configured to output N sets of the M random number sequences including N different relative time differences or N different combinations of a plurality of relative time differences, where N is an integer greater than or equal to 2, by adjusting one or more relative time differences between the M random number sequences, and a logic operation circuit configured to perform an exclusive OR operation between the M random number sequences included in a set, for each of the N sets of the M random number sequences.

Abstract: An apparatus identifies each of one or more strongly connected graphs included in a control flow graph of a program, and calculates a characteristic value indicating a characteristic of a first process indicated by the identified strongly connected graph, based on profile information indicating a characteristic of a second process indicated by each of one or more nodes included in the control flow graph. The apparatus determines, based on the calculated characteristic value of the first process and a requirement set for an accelerator, whether or not the first process is executable by the accelerator.

Abstract: A simulation apparatus includes a memory and a processor. The processor is configured to: acquire a circuit model described in a hardware description language; extract a reading and writing relationship between a process and a register variable included in the circuit model; determine an evaluation order of the process, based on the number of register variables whose extracted relationship satisfies a given condition; and convert, into a blocking variable, a register variable which satisfies the given condition in the determined evaluation order of the process among the register variables included in the circuit model.

Abstract: An information processing apparatus includes a memory; and a processor coupled to the memory and the processor that creates module partitioning candidates of a plurality of software codes including one or more input nodes from a plurality of input nodes in a data flow graph and calculates a cost corresponding to a bit width of a signal line of the module partitioning candidates for each of the created plurality of module partitioning candidates, and selects one or more module partitioning candidates having a given cost from the plurality of module partitioning candidates as a partitioning target module based on the calculated cost.

Abstract: A simulation apparatus includes a memory and a processor. The processor is configured to: acquire a circuit model described in a hardware description language; extract a reading and writing relationship between a process and a register variable included in the circuit model; determine an evaluation order of the process, based on the number of register variables whose extracted relationship satisfies a given condition; and convert, into a blocking variable, a register variable which satisfies the given condition in the determined evaluation order of the process among the register variables included in the circuit model.

Abstract: An apparatus includes an arithmetic circuit that performs a pipeline operation on first data as an input; and a determination circuit that determines, based on pipeline operation results, whether to perform the pipeline operation by inputting, to the arithmetic circuit, second data different from the first data, wherein when the determination circuit has determined that the pipeline operation is to be performed by inputting the second data to the arithmetic circuit, the arithmetic circuit suspends the pipeline operation using the second data thereof, and performs the pipeline operation with the first data input until the second data is input, and when the second data is input, the arithmetic circuit resumes the pipeline operation using the second data.

Abstract: A random number generating circuit includes M random number generators, where M is an integer greater than or equal to 2, configured to be independent of each other and generate M random number sequences, a delay adjustment circuit configured to output N sets of the M random number sequences including N different relative time differences or N different combinations of a plurality of relative time differences, where N is an integer greater than or equal to 2, by adjusting one or more relative time differences between the M random number sequences, and a logic operation circuit configured to perform an exclusive OR operation between the M random number sequences included in a set, for each of the N sets of the M random number sequences.

Abstract: A SystemC model generation method includes: analyzing a hardware description language (HDL) behavioral model which is designed with an HDL simulation syntax to generate a syntax tree model; analyzing the syntax tree model to extract analysis information; and reconstructing the syntax tree model based on the syntax tree model and the analysis information to generate a SystemC model which is capable of high-level synthesis.

Abstract: An information processing apparatus includes a memory; and a processor coupled to the memory and the processor that creates module partitioning candidates of a plurality of software codes including one or more input nodes from a plurality of input nodes in a data flow graph and calculates a cost corresponding to a bit width of a signal line of the module partitioning candidates for each of the created plurality of module partitioning candidates, and selects one or more module partitioning candidates having a given cost from the plurality of module partitioning candidates as a partitioning target module based on the calculated cost.

Abstract: An apparatus identifies each of one or more strongly connected graphs included in a control flow graph of a program, and calculates a characteristic value indicating a characteristic of a first process indicated by the identified strongly connected graph, based on profile information indicating a characteristic of a second process indicated by each of one or more nodes included in the control flow graph. The apparatus determines, based on the calculated characteristic value of the first process and a requirement set for an accelerator, whether or not the first process is executable by the accelerator.

Abstract: A memory control apparatus including at least one buffer memory and a processor coupled to the at least one buffer memory, and the processor configured to execute a process including receiving pieces of data to be written to a memory device, each of the pieces of data being associated with an index indicating a position of memory region of in the memory device, storing the pieces of data to the at least one buffer memory, sorting the pieces of data stored in the at least one buffer memory in accordance with the index, write the pieces of data sorted in the at least one buffer memory to the memory device at once, by using a block access function that writes plural pieces of data each of which the position indicated by the index is included in the predetermined index range.

Abstract: An apparatus includes an arithmetic circuit that performs a pipeline operation on first data as an input; and a determination circuit that determines, based on pipeline operation results, whether to perform the pipeline operation by inputting, to the arithmetic circuit, second data different from the first data, wherein when the determination circuit has determined that the pipeline operation is to be performed by inputting the second data to the arithmetic circuit, the arithmetic circuit suspends the pipeline operation using the second data thereof, and performs the pipeline operation with the first data input until the second data is input, and when the second data is input, the arithmetic circuit resumes the pipeline operation using the second data.

Abstract: A memory unit stores first and second code values calculated by encoding a first sequence, contained in a first word, and a remaining second sequence of a target sequence, and the number of bytes from a word start to a target sequence start. A code value calculating unit calculates a code value for each byte, based on signal sequence. A first sequence detecting unit detects the first sequence, by comparing the first code value with a difference between the code values at the last byte of a word and at the byte corresponding to the number of bytes. An expected value calculating unit calculates an expected code value at the target sequence end, based on the code value at detection of the first sequence and the second code value. A determination unit signals that the target sequence is detected, when the code value equals the expected value.

Abstract: A debugging circuit including: a storage configured to store a first code value which is calculated by an encoding method in which a value is changed according to a sequence of a signal in a debugging target circuit, and indicates a stop condition of the debugging target circuit; a code value calculator configured to calculate a second code value by the encoding method based on the signal each time when the signal is changed; and an operation stopper configured to stop an operation of the debugging target circuit when the first code value and the second code value are identical to each other.

Abstract: A debug circuit, includes: a controller to start a debugging of a circuit based on first and second code values, the first code value obtained by encoding a first sequence included in a processing sequence indicating a condition for a process of the circuit, the second code value obtained by encoding a second sequence subsequent to the first sequence, wherein the controller performs to: calculate a third code value as a current code value based on signals input and output to the circuit; output, as a fourth code value, a previous third code value that is earlier than the current code value; detect the first sequence by comparing a difference between the third code value and the fourth code value with the first code value; calculate a first expected value of the third code value; and perform the process when the third code value and the first expected value match.

Abstract: A circuit includes don't-care a code-value calculation circuit to calculate third code-values by coding a signal sequence in accordance with a coding scheme; a first sequence-detection circuit to detect a first sequence based on comparison of a first code-value with a difference between the current third code-value and a fourth code-value that is the third code-value preceding the current third code-value by a length of the first sequence; an expected-value calculation circuit to calculate an expected value of the third code-value at the end of the third sequence based on a second code-value and a fifth code-value that is one of the third code-values; and a determination circuit to detect the end of the second sequence based on a length of a fourth sequence, notify an expected-value calculation circuit of the detection of the second sequence, and output a detection signal indicating detection of a detection-target sequence.