Abstract: An effective data amount and a power index of a module selected from a design target circuit are extracted from a time-series table database (DB) for each clock cycle. Time periods during which the effective data amount is “0” and there is a high possibility of improving power consumption, are identified. It is determined whether a first simulation result from the design target circuit and a second simulation result from the design target circuit into which a control circuit has been inserted to stop supplying a clock to the module continuously for the identified time periods coincide. Then, if the first simulation result and the second simulation result coincide, the time periods are determined as targets to which a clock gating is applicable.

Abstract: A non-transitory, computer-readable recording medium stores therein a verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition>the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in

Abstract: A non-transitory recording medium has a scheduler program embodied therein for controlling parallel execution of plural simulation programs, the scheduler program causing a computer to perform a parallel execution procedure by which the plural simulation programs are performed in parallel during a period in which there is no data exchange between the plural simulation programs, and a sequential execution procedure by which the plural simulation programs are sequentially performed during a period in which there is data exchange between the plural simulation programs.

Abstract: A method includes causing a circuit simulator to perform a circuit simulation using circuit data stored in a storage, the circuit data containing a module to be modeled and a circuit for making a change to a clock to be inputted into the module and clock setting data stored in a storage, the clock setting data being intended to, at a predetermined timing, make a change to the clock to be inputted into the module, and storing a result of the circuit simulation in a simulation result data storage; and generating a hidden markov model about input and output signals of the module from values and times of the signals in accordance with a predetermined algorithm, the values and times being contained in the circuit simulation result stored in the simulation result data storage, and storing data about the model in a hidden markov model data storage.

Abstract: A circuit module includes a shift register constituting part of a scan chain within a semiconductor integrated circuit, a control unit for controlling an operation of the shift register using a control signal generated within the semiconductor integrated circuit and a selection unit for selecting between a short-circuit path through which a scan signal is loaded and an ordinary path through which the scan signal is loaded after being made to go through the shift register, where the ordinary path is selected when the operation of the shift register is permitted by the control signal and the short-circuit path is selected when the operation of the shift register is not permitted.

Abstract: An effective data amount and a power index of a module selected from a design target circuit are extracted from a time-series table DB for each clock cycle. Time periods during which the effective data amount is “0” and there is a high possibility of improving power consumption, are identified. It is determined whether a first simulation result from the design target circuit and a second simulation result from the design target circuit into which a control circuit has been inserted to stop the supply of a clock to the module continuously for the identified time periods coincide. Then, if the first and the second simulation results coincide, the time periods are determined as targets to which clock gating is applicable.

Abstract: A power index computing apparatus that computes a power index for a circuit having one or more modules includes an obtaining unit that obtains estimated power consumption for a module in the circuit and a first computing unit that computes entropy based on a transition probability of an output signal of the module during a simulation period. The entropy is indicative of an expected value of a data volume output from the module, and the output signal is output to a destination that is external to the module. The power index computing apparatus further includes a second computing unit that computes a power index based on the estimated power consumption and the entropy, where the power index concerns power consumption for output of the output signal with respect to the estimated power consumption. An output unit of the power index apparatus outputs a result of the second computing unit.

Abstract: An information input unit inputs functional configuration information representing a function of a device to be validated. A condition input unit inputs conditions concerning input/output sequence that is given to the device. A function generation unit generates a validation item function that fulfills all of the conditions based on the functional configuration information. An extraction unit extracts a combination of configuration elements that constitute the functional configuration information as a validation item based on the validation item function.

Abstract: According to an aspect of an embodiment, an evaluation device for evaluating a target program is provided by calculating a first parameter showing an impact size of a target module of the target program on the outside of the target module, based on an execution log of the target program and calculating a second parameter that is a value related to a power consumption by executing the target module. An evaluator evaluates the target module based on the first and second parameters and outputs an evaluation result.

Abstract: An information input unit inputs functional configuration information representing a function of a device to be validated. A condition input unit inputs conditions concerning input/output sequence that is given to the device. A function generation unit generates a validation item function that fulfills all of the conditions based on the functional configuration information. An extraction unit extracts a combination of configuration elements that constitute the functional configuration information as a validation item based on the validation item function.

Abstract: A network analyzing method for analyzing an arrival time at each node of a network having at least one false path so as to perform a delay analysis and optimize the network, comprising the step of providing a plurality of arrival time variables, including an arrival time with respect to the false path and an arrival time without respect to the false path, for each node on the false path.