Abstract: In a multiplexer circuit which loads N data segments (N is an integer of N<M) led by an arbitrary data segment from a first register storing M data segments (M is an integer equal to or larger than two) to a second register, an intermediate register is disposed between the first register and the second register. A first selection circuit between the first register and the intermediate register and a second selection circuit between the intermediate register and the second register are designed based on a value of L for minimizing a circuit amount of the first selection circuit and the second selection circuit. The value of L for minimizing the circuit amount is calculated based on values of the M and the N. Therefore, it is possible to reduce the circuit amount of the multiplexer circuit capable of performing data access with respect to large-volume data.

Abstract: A circuit includes don't-care a code-value calculation circuit to calculate third code-values by coding a signal sequence in accordance with a coding scheme; a first sequence-detection circuit to detect a first sequence based on comparison of a first code-value with a difference between the current third code-value and a fourth code-value that is the third code-value preceding the current third code-value by a length of the first sequence; an expected-value calculation circuit to calculate an expected value of the third code-value at the end of the third sequence based on a second code-value and a fifth code-value that is one of the third code-values; and a determination circuit to detect the end of the second sequence based on a length of a fourth sequence, notify an expected-value calculation circuit of the detection of the second sequence, and output a detection signal indicating detection of a detection-target sequence.

Abstract: A memory unit stores first and second code values calculated by encoding a first sequence, contained in a first word, and a remaining second sequence of a target sequence, and the number of bytes from a word start to a target sequence start. A code value calculating unit calculates a code value for each byte, based on signal sequence. A first sequence detecting unit detects the first sequence, by comparing the first code value with a difference between the code values at the last byte of a word and at the byte corresponding to the number of bytes. An expected value calculating unit calculates an expected code value at the target sequence end, based on the code value at detection of the first sequence and the second code value. A determination unit signals that the target sequence is detected, when the code value equals the expected value.

Abstract: A waveform analyzer includes a converter which converts a logical function, where a pair of data including a time and a value at the time is variable, created according to data sets of a time and a value of a signal waveform at the time into a second function expressed by a binary decision diagram, an acquisition unit which obtains for each of characteristic points of a reference waveform a condition representative of constraints on a relationship between time information specified by the points and a value corresponding to the time information in the signal waveform according to a value of the reference waveform at the points and a specified tolerance given to a value of the reference waveform, and a searching unit which applies the condition for each of the points to the second function to obtain a time range which meets the entirety of the conditions.

Abstract: A debug circuit, includes: a controller to start a debugging of a circuit based on first and second code values, the first code value obtained by encoding a first sequence included in a processing sequence indicating a condition for a process of the circuit, the second code value obtained by encoding a second sequence subsequent to the first sequence, wherein the controller performs to: calculate a third code value as a current code value based on signals input and output to the circuit; output, as a fourth code value, a previous third code value that is earlier than the current code value; detect the first sequence by comparing a difference between the third code value and the fourth code value with the first code value; calculate a first expected value of the third code value; and perform the process when the third code value and the first expected value match.

Abstract: A debugging circuit including: a storage configured to store a first code value which is calculated by an encoding method in which a value is changed according to a sequence of a signal in a debugging target circuit, and indicates a stop condition of the debugging target circuit; a code value calculator configured to calculate a second code value by the encoding method based on the signal each time when the signal is changed; and an operation stopper configured to stop an operation of the debugging target circuit when the first code value and the second code value are identical to each other.

Abstract: In a multiplexer circuit which loads N data segments (N is an integer of N<M) led by an arbitrary data segment from a first register storing M data segments (M is an integer equal to or larger than two) to a second register, an intermediate register is disposed between the first register and the second register. A first selection circuit between the first register and the intermediate register and a second selection circuit between the intermediate register and the second register are designed based on a value of L for minimizing a circuit amount of the first selection circuit and the second selection circuit. The value of L for minimizing the circuit amount is calculated based on values of the M and the N. Therefore, it is possible to reduce the circuit amount of the multiplexer circuit capable of performing data access with respect to large-volume data.

Abstract: A communication device includes a memory and a processor coupled to the memory. The processor executes a process including calculating an amount of electricity available in a second device while a first communication unit and a second communication unit with each other, determining a first generation unit to be a generation unit, when the amount of electricity thus calculated is smaller than a predetermined amount, out of the first generation unit that generates navigation information based on information acquired by an information acquisition unit and a second generation unit, and controlling the second device so as to stop supplying power to the second generation unit and to output the navigation information generated by the first generation unit when the first generation unit is determined.

Abstract: A non-transitory, computer-readable recording medium stores therein a verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition>the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in

Abstract: A non-transitory, computer-readable recording medium stores therein a verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition>the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in

Abstract: A verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition is greater than the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in the test scenario group.

Abstract: A circuit module includes a shift register constituting part of a scan chain within a semiconductor integrated circuit, a control unit for controlling an operation of the shift register using a control signal generated within the semiconductor integrated circuit and a selection unit for selecting between a short-circuit path through which a scan signal is loaded and an ordinary path through which the scan signal is loaded after being made to go through the shift register, where the ordinary path is selected when the operation of the shift register is permitted by the control signal and the short-circuit path is selected when the operation of the shift register is not permitted.

Abstract: A non-transitory recording medium has a scheduler program embodied therein for controlling parallel execution of plural simulation programs, the scheduler program causing a computer to perform a parallel execution procedure by which the plural simulation programs are performed in parallel during a period in which there is no data exchange between the plural simulation programs, and a sequential execution procedure by which the plural simulation programs are sequentially performed during a period in which there is data exchange between the plural simulation programs.

Abstract: A communication device includes a memory and a processor coupled to the memory. The processor executes a process including calculating an amount of electricity available in a second device while a first communication unit and a second communication unit with each other, determining a first generation unit to be a generation unit, when the amount of electricity thus calculated is smaller than a predetermined amount, out of the first generation unit that generates navigation information based on information acquired by an information acquisition unit and a second generation unit, and controlling the second device so as to stop supplying power to the second generation unit and to output the navigation information generated by the first generation unit when the first generation unit is determined.

Abstract: A method includes causing a circuit simulator to perform a circuit simulation using circuit data stored in a storage, the circuit data containing a module to be modeled and a circuit for making a change to a clock to be inputted into the module and clock setting data stored in a storage, the clock setting data being intended to, at a predetermined timing, make a change to the clock to be inputted into the module, and storing a result of the circuit simulation in a simulation result data storage; and generating a hidden markov model about input and output signals of the module from values and times of the signals in accordance with a predetermined algorithm, the values and times being contained in the circuit simulation result stored in the simulation result data storage, and storing data about the model in a hidden markov model data storage.

Abstract: A waveform analyzer includes a converter which converts a logical function, where a pair of data including a time and a value at the time is variable, created according to data sets of a time and a value of a signal waveform at the time into a second function expressed by a binary decision diagram, an acquisition unit which obtains for each of characteristic points of a reference waveform a condition representative of constraints on a relationship between time information specified by the points and a value corresponding to the time information in the signal waveform according to a value of the reference waveform at the points and a specified tolerance given to a value of the reference waveform, and a searching unit which applies the condition for each of the points to the second function to obtain a time range which meets the entirety of the conditions.

Abstract: According to an aspect of an embodiment, an evaluation device for evaluating a target program is provided by calculating a first parameter showing an impact size of a target module of the target program on the outside of the target module, based on an execution log of the target program and calculating a second parameter that is a value related to a power consumption by executing the target module. An evaluator evaluates the target module based on the first and second parameters and outputs an evaluation result.

Abstract: A computer-readable, non-transitory medium saving a debugging support program representing a sequence of instructions, the program which is executable by a target computer to perform receiving a connection request for remotely debugging a process, of which an identifier is designated for the remote debugging, using a host computer; searching a plurality of processes activated in the target computer for the process having the designated identifier; and connecting the target computer to the host computer to enable remotely debugging the searched process having the designated identifier.

Abstract: A computer-readable, non-transitory medium storing a simulation program that causes a computer to execute a distributed processing by cooperating with a scheduler and another simulation program including: resuming, when a continuation instruction is received from the scheduler, the distributed processing; suspending, when a predetermined time passes after the resuming, the distributed processing; reporting the suspending to the scheduler; generating, when a read or write request of data is received from the other simulation program, a process for processing the read or write request of the data; and processing the read or write request of the data by the process.

Abstract: A power index computing apparatus that computes a power index for a circuit having one or more modules includes an obtaining unit that obtains estimated power consumption for a module in the circuit and a first computing unit that computes entropy based on a transition probability of an output signal of the module during a simulation period. The entropy is indicative of an expected value of a data volume output from the module, and the output signal is output to a destination that is external to the module. The power index computing apparatus further includes a second computing unit that computes a power index based on the estimated power consumption and the entropy, where the power index concerns power consumption for output of the output signal with respect to the estimated power consumption. An output unit of the power index computing apparatus outputs a result of the second computing unit.