Patents by Inventor Zhenrong Jin
Zhenrong Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170338827Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.Type: ApplicationFiled: August 4, 2017Publication date: November 23, 2017Inventors: Jingdong Deng, Chung S. Ho, David FLYE, Zhenrong JIN, Ramana M. MALLADI
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Patent number: 9819350Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.Type: GrantFiled: August 26, 2016Date of Patent: November 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jingdong Deng, Chung S. Ho, David Flye, Zhenrong Jin, Ramana M. Malladi
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Patent number: 9806723Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.Type: GrantFiled: August 26, 2016Date of Patent: October 31, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jingdong Deng, Chung S. Ho, David Flye, Zhenrong Jin, Ramana M. Malladi
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Publication number: 20160365864Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.Type: ApplicationFiled: August 26, 2016Publication date: December 15, 2016Inventors: Jingdong DENG, Chung S. HO, David S. FLYE, Zhenrong JIN, Ramana M. MALLADI
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Publication number: 20160365862Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.Type: ApplicationFiled: August 26, 2016Publication date: December 15, 2016Inventors: Jingdong DENG, Chung S. HO, David S. FLYE, Zhenrong JIN, Ramana M. MALLADI
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Publication number: 20160365863Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.Type: ApplicationFiled: August 26, 2016Publication date: December 15, 2016Inventors: Jingdong DENG, Chung S. HO, David S. FLYE, Zhenrong JIN, Ramana M. MALLADI
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Publication number: 20160365861Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.Type: ApplicationFiled: August 26, 2016Publication date: December 15, 2016Inventors: Jingdong DENG, Chung S. HO, David S. FLYE, Zhenrong JIN, Ramana M. MALLADI
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Patent number: 9455728Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.Type: GrantFiled: April 4, 2014Date of Patent: September 27, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jingdong Deng, Chung S. Ho, David Flye, Zhenrong Jin, Ramana M. Malladi
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Patent number: 9252717Abstract: An approach for a transconductance cell for use in a voltage controlled oscillator (VCO) is provided. The transconductance cell includes a first NFET stack connected in series to a first PFET stack. The transconductance cell includes a second NFET stack connected in series to a second PFET stack. The first NFET stack and the first PFET stack are cross-coupled to the second NFET stack and the second PFET stack. The first NFET stack and the second NFET stack are connected to a tail node. The first PFET stack and the second PFET stack are connected to a power supply node.Type: GrantFiled: June 4, 2014Date of Patent: February 2, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Anthony R. Bonaccio, Zhenrong Jin, Ram Kelkar, Anjali R. Malladi, Ramana M. Malladi
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Publication number: 20150357977Abstract: An approach for a transconductance cell for use in a voltage controlled oscillator (VCO) is provided. The transconductance cell includes a first NFET stack connected in series to a first PFET stack. The transconductance cell includes a second NFET stack connected in series to a second PFET stack. The first NFET stack and the first PFET stack are cross-coupled to the second NFET stack and the second PFET stack. The first NFET stack and the second NFET stack are connected to a tail node. The first PFET stack and the second PFET stack are connected to a power supply node.Type: ApplicationFiled: June 4, 2014Publication date: December 10, 2015Inventors: Anthony R. BONACCIO, Zhenrong JIN, Ram KELKAR, Anjali R. MALLADI, Ramana M. MALLADI
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Publication number: 20150288370Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.Type: ApplicationFiled: April 4, 2014Publication date: October 8, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jingdong DENG, Chung S. HO, David FLYE, Zhenrong JIN, Ramana M. MALLADI
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Publication number: 20140253169Abstract: A type of device (which can be deployed in a semiconductor manufacturing line) determining whether a device-under-test is generating burst noise. A transimpedance amplifier converts a current-based noise signal to a voltage based noise signal to apply the following tests aimed at determining the presence of burst noise: (i) sufficiently wide pulse width in the noise signal; (ii) sufficiently random pulse width in the noise signal; (iii) sufficiently wide pulse separation in the noise signal; (iv) sufficiently random pulse separation in the noise signal; and (v) sufficiently large pulse amplitude (or magnitude) in the noise signal.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai D. Feng, Zhenrong Jin
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Patent number: 8791728Abstract: A dynamic latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. An inverter receives the updated data signal from the pass gate, and inverts and outputs the updated data signal as an output data signal. Thus, the dynamic latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal. The four logical operations are performed using the signals applied to the two inputs.Type: GrantFiled: October 18, 2011Date of Patent: July 29, 2014Assignee: International Business Machines CorporationInventors: John S. Austin, Kai D. Feng, Shiu Chung Ho, Zhenrong Jin
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Patent number: 8791726Abstract: Recycling energy in a clock distribution network is provided. A circuit includes a clock driver associated with a clock signal and having an output connected to a first load capacitance. The circuit also includes a second load capacitance connected in parallel with the first load capacitance. The circuit further includes a power transfer circuit including an inductor and a transmission gate connected in series between the first load capacitance and the second load capacitance. The power transfer circuit controls a flow of energy between the first load capacitance and the second load capacitance based on the clock signal.Type: GrantFiled: January 3, 2013Date of Patent: July 29, 2014Assignee: International Business Machines CorporationInventors: Anthony R. Bonaccio, Jingdong Deng, Zhenrong Jin
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Publication number: 20140184295Abstract: Recycling energy in a clock distribution network is provided. A circuit includes a clock driver associated with a clock signal and having an output connected to a first load capacitance. The circuit also includes a second load capacitance connected in parallel with the first load capacitance. The circuit further includes a power transfer circuit including an inductor and a transmission gate connected in series between the first load capacitance and the second load capacitance. The power transfer circuit controls a flow of energy between the first load capacitance and the second load capacitance based on the clock signal.Type: ApplicationFiled: January 3, 2013Publication date: July 3, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony R. BONACCIO, Jingdong DENG, Zhenrong JIN
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Patent number: 8581648Abstract: A method includes phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of a the PLL circuit. A circuit includes: a first phase lock loop (PLL) circuit and a second PLL circuit referenced to a same clock; a phase detector circuit that detects a phase difference between an output signal of the first PLL circuit and an output signal of the second PLL circuit; and an adjustable current source that applies an injection current to at least one of the first PLL circuit and the second PLL circuit based on an output of the phase detector circuit.Type: GrantFiled: February 7, 2013Date of Patent: November 12, 2013Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Zhenrong Jin, Francis F. Szenher
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Patent number: 8525561Abstract: A phase lock loop (PLL) includes a PLL feedback circuit having a feedback divider. The feedback divider has a first dynamic latch, a first logic circuit, and a plurality of serially connected dynamic latches. Each of the serially connected dynamic latches receives and forwards additional data signals to subsequent ones of the serially connected dynamic latches in series. The second-to-last dynamic latch in the series outputs a fourth data signal to a last dynamic latch in the series. The last dynamic latch receives the fourth data signal and outputs a fifth data signal. A first feedback loop receives the fourth data signal from the second-to-last dynamic latch and the fifth data signal from the last dynamic latch. The first feedback loop comprises a NAND circuit that combines the fourth and fifth data signals and the first feedback loop outputs the first feedback signal.Type: GrantFiled: October 18, 2011Date of Patent: September 3, 2013Assignee: International Business Machines CorporationInventors: John S. Austin, Kai D. Feng, Shiu Chung Ho, Zhenrong Jin
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Patent number: 8519892Abstract: A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.Type: GrantFiled: June 27, 2012Date of Patent: August 27, 2013Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Zhong-Xiang He, Zhenrong Jin, Xuefeng Liu
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Patent number: 8471595Abstract: A selectable latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. The output of the parallel pass gates and the additional pass gate is connected to a feedback loop. The feedback loop operates as a dynamic latch for high frequency applications or as a static latch for low frequency applications. Thus, the selectable latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal.Type: GrantFiled: January 19, 2012Date of Patent: June 25, 2013Assignee: International Business Machines CorporationInventors: John S. Austin, Kai D. Feng, Shiu Chung Ho, Zhenrong Jin, Michael R. Ouellette
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Publication number: 20130093481Abstract: A phase lock loop (PLL) includes a PLL feedback circuit having a feedback divider. The feedback divider has a first dynamic latch, a first logic circuit, and a plurality of serially connected dynamic latches. Each of the serially connected dynamic latches receives and forwards additional data signals to subsequent ones of the serially connected dynamic latches in series. The second-to-last dynamic latch in the series outputs a fourth data signal to a last dynamic latch in the series. The last dynamic latch receives the fourth data signal and outputs a fifth data signal. A first feedback loop receives the fourth data signal from the second-to-last dynamic latch and the fifth data signal from the last dynamic latch. The first feedback loop comprises a NAND circuit that combines the fourth and fifth data signals and the first feedback loop outputs the first feedback signal.Type: ApplicationFiled: October 18, 2011Publication date: April 18, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John S. Austin, Kai D. Feng, Shiu Chung Ho, Zhenrong Jin