Abstract: A dynamic latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. An inverter receives the updated data signal from the pass gate, and inverts and outputs the updated data signal as an output data signal. Thus, the dynamic latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal. The four logical operations are performed using the signals applied to the two inputs.

Abstract: A method includes phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of a the PLL circuit. A circuit includes: a first phase lock loop (PLL) circuit and a second PLL circuit referenced to a same clock; a phase detector circuit that detects a phase difference between an output signal of the first PLL circuit and an output signal of the second PLL circuit; and an adjustable current source that applies an injection current to at least one of the first PLL circuit and the second PLL circuit based on an output of the phase detector circuit.

Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

Abstract: Embodiments of the present invention provide an approach for receiving true and complement clock signals at high or low frequencies into inputs of a divide-by-two quadrature divider, and providing true and complement clock signals, which are one-half the measured frequencies of the clock input signals, at the output of the quadrature divider. A tri-state clock mux coupled with combinatorial reset logic, with pull-up and pull-down devices at the output of the tri-sate clock mux, and/or pull-up and pull-down devices between the quadrature divider latches provide a defined logic state during startup at the input of the quadrature divider. The defined logic state ensures the output of the quadrature divider is metastability-free during high frequency application. Specifically, the quadrature divider has two output clock signals that are true and complement with measured frequencies that are one-half of the measured frequencies of the two clock input signals coming into the quadrature divider.

Abstract: A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.

Abstract: A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.

Abstract: Embodiments of the present invention provide an approach for receiving true and complement clock signals at high or low frequencies into inputs of a divide-by-two quadrature divider, and providing true and complement clock signals, which are one-half the measured frequencies of the clock input signals, at the output of the quadrature divider. A tri-state clock mux coupled with combinatorial reset logic, with pull-up and pull-down devices at the output of the tri-sate clock mux, and/or pull-up and pull-down devices between the quadrature divider latches provide a defined logic state during startup at the input of the quadrature divider. The defined logic state ensures the output of the quadrature divider is metastability-free during high frequency application. Specifically, the quadrature divider has two output clock signals that are true and complement with measured frequencies that are one-half of the measured frequencies of the two clock input signals coming into the quadrature divider.

Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

Abstract: A method includes phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of a the PLL circuit. A circuit includes: a first phase lock loop (PLL) circuit and a second PLL circuit referenced to a same clock; a phase detector circuit that detects a phase difference between an output signal of the first PLL circuit and an output signal of the second PLL circuit; and an adjustable current source that applies an injection current to at least one of the first PLL circuit and the second PLL circuit based on an output of the phase detector circuit.

Abstract: A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.

Abstract: A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is formed on a front side of a semiconductor substrate. At least one through substrate via provides electrical connection between the transceiver and the backside of the semiconductor substrate. The antenna, which is connected to the transceiver, is formed in a dielectric layer on the front side. The reflector plate is connected to the through substrate via, and is formed on the backside. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate trenches may be formed and filled with a dielectric material to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency.

Abstract: Methods for selecting one or more golden devices on a golden wafer that exhibit a smooth length and width scaling behavior. Test devices of differing geometry and carried on different chips of the golden wafer are screened with single point measurements of electrical performance. Based upon a statistical analysis of these single point measurements, chips are selected that carry the respective golden device of each given geometry that exhibits optimum electrical performance referenced to a selection criterion. Golden devices identified by the selection process are extensively characterized with a more comprehensive electrical measurement. The parameters derived from these more extensive test measurements on the golden devices are then used for refining a device model for a circuit simulation.

Abstract: S-parameter data is measured on an embedded device test structure, an open dummy, and a short dummy. A 4-port network of the pad set parasitics of the embedded device test structure is modeled by a parameterized netlist containing a lumped element network having at least one parameterized lumped element. The S-parameter data across a range of measurement frequencies is fitted with the parameterized netlist employing the at least one parameterized lumped element as at least one fitting parameter for the S-parameter data. Thus, the fitting method is a multi-frequency fitting for the at least one parameterized lumped element. A 4-port Y-parameter (admittance parameter) is obtained from the fitted parameterized netlist. The Y-parameter of the device under test is obtained from the measured admittance of the embedded device test structure and the calculated 4-port Y parameter.

Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

Abstract: A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.

Abstract: A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.

Abstract: A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is formed on a front side of a semiconductor substrate. At least one through substrate via provides electrical connection between the transceiver and the backside of the semiconductor substrate. The antenna, which is connected to the transceiver, is formed in a dielectric layer on the front side. The reflector plate is connected to the through substrate via, and is formed on the backside. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate trenches may be formed and filled with a dielectric material to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency.

Abstract: A design structure for designing, manufacturing, and/or testing a frequency divider and monitoring circuit. The circuit including a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedback frequency divider, and output of the feedback frequency divider coupled to an input of the voltage controlled oscillator; and a frequency divider monitor having a first input, a second input and an output, the first input of the frequency divider monitor connected to the output of the voltage controlled oscillator and the second input of the frequency divider monitor coupled to an output of the feedback frequency divider.

Abstract: S-parameter data is measured on an embedded device test structure, an open dummy, and a short dummy. A 4-port network of the pad set parasitics of the embedded device test structure is modeled by a parameterized netlist containing a lumped element network having at least one parameterized lumped element. The S-parameter data across a range of measurement frequencies is fitted with the parametrized netlist employing the at least one parameterized lumped element as at least one fitting parameter for the S-parameter data. Thus, the fitting method is a multi-frequency fitting for the at least one parameterized lumped element. A 4-port Y-parameter (admittance parameter) is obtained from the fitted parameterized netlist. The Y-parameter of the device under test is obtained from the measured admittance of the embedded device test structure and the calculated 4-port Y parameter.