Patents by Inventor Zhihai Wang

Zhihai Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6028015
    Abstract: A process is described for treating damaged surfaces of a low dielectric constant organo silicon oxide insulation layer of an integrated circuit structure to inhibit absorption of moisture which comprises treating such damaged surfaces of said organo silicon oxide insulation layer with a hydrogen plasma. The treatment with hydrogen plasma causes hydrogen to bond to silicon atoms with dangling bonds in the damaged surface of the organo silicon oxide layer to replace organic material severed from such silicon atoms at the damaged surface, whereby absorption of moisture in the damaged surface of the organo silicon oxide layer, by bonding of such silicon dangling bonds with moisture, is inhibited.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: February 22, 2000
    Assignee: LSI Logic Corporation
    Inventors: Zhihai Wang, Wilbur G. Catabay, Joe W. Zhao
  • Patent number: 6010952
    Abstract: An improved process is provided for amorphizing portions of a silicon substrate and a polysilicon gate electrode surface to be converted to metal silicide by subsequent reaction of the amorphized silicon with a metal layer applied over the silicon substrate and polysilicon gate electrode after the amorphizing step. The improvement comprises implanting the exposed surface of the silicon substrate and the surface of the polysilicon gate electrode with a beam of amorphizing ions at an angle of at least 15.degree. to a line perpendicular to the plane of the surface of the silicon substrate to thereby inhibit channeling of the implanted ions through the gate electrode to the underlying gate oxide and channel of the MOS structure. The implant angle of the beam of amorphizing ions is preferably at least 30.degree., but should not exceed 60.degree., with respect to a line perpendicular to the plane of the surface of the silicon substrate.
    Type: Grant
    Filed: January 23, 1997
    Date of Patent: January 4, 2000
    Assignee: LSI Logic Corporation
    Inventors: Jiunn-Yann Tsai, Zhihai Wang, Wen-Chin Yeh
  • Patent number: 5994211
    Abstract: Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.
    Type: Grant
    Filed: November 21, 1997
    Date of Patent: November 30, 1999
    Assignee: LSI Logic Corporation
    Inventors: Zhihai Wang, Wei-Jen Hsia, Wilbur Catabay
  • Patent number: 5902129
    Abstract: The formation of a cobalt silicide layer of uniform thickness over the source/drain regions and the polysilicon gate electrode of an MOS structure, which does not thin out adjacent the edges of the top surface of the polysilicon gate electrode, i.e., adjacent the oxide spacers, is achieved by first forming a titanium capping layer over a cobalt layer deposited over the MOS structure prior to formation of the cobalt silicide, and while excluding oxygen-bearing gases from the cobalt surface prior to the deposition of the titanium capping layer.
    Type: Grant
    Filed: April 7, 1997
    Date of Patent: May 11, 1999
    Assignee: LSI Logic Corporation
    Inventors: Stephanie A. Yoshikawa, Zhihai Wang, Wilbur G. Catabay
  • Patent number: 5874342
    Abstract: A process which is capable of forming shallow source/drain regions in a silicon substrate and a doped gate electrode by implantation of cobalt silicide contacts of uniform thickness previously formed on the substrate followed by diffusion of the dopant into the substrate to form the desired source/drain regions, and into the polysilicon gate electrode to provide the desired conductivity is described.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: February 23, 1999
    Assignee: LSI Logic Corporation
    Inventors: Jiunn-Yann Tsai, Zhihai Wang, Yen-Hui Joseph Ku
  • Patent number: 5770520
    Abstract: Described is a barrier layer in an integrated circuit structure which is formed in a via or contact opening over an underlying material in which diffusion of the underlying material (or filler material deposited over the barrier layer) through the barrier layer is inhibited without unduly increasing the thickness and resistivity of the barrier layer. This is accomplished by substituting an amorphous material for the crystalline titanium nitride to thereby eliminate the present of grain boundaries which are believed to provide the diffusion path through the titanium nitride material. In a preferred embodiment, the amorphous barrier layer comprises an amorphous ternary Ti--Si--N material formed using a source of titanium, a source of silicon, and a source of nitrogen. None of the source materials should contain oxygen to avoid formation of undesirable oxides which would increase the resistivity of the barrier layer.
    Type: Grant
    Filed: December 5, 1996
    Date of Patent: June 23, 1998
    Assignee: LSI Logic Corporation
    Inventors: Joe W. Zhao, Zhihai Wang, Wilbur G. Catabay
  • Patent number: 5660682
    Abstract: A method of removing material from an integrated circuit. The integrated circuit is placed within a reaction chamber, and a flow of argon and a flow of hydrogen are introduced into the reaction chamber, where the flow of hydrogen is greater than the flow of argon. The flows of argon and hydrogen are energized to form a plasma, and the material is removed from the integrated circuit by reaction of the material with the energized flows of argon and hydrogen to form gaseous products, which are pumped out of the reaction chamber. The plasma and flows of argon and hydrogen are discontinued when a desired amount of material has been removed, and the integrated circuit is removed from the reaction chamber.
    Type: Grant
    Filed: March 14, 1996
    Date of Patent: August 26, 1997
    Assignee: LSI Logic Corporation
    Inventors: Joe W. Zhao, Zhihai Wang, Wilbur G. Catabay
  • Patent number: 5364186
    Abstract: A blackbody high temperature probe is formed by thermally fusing a coating of composite ceramic material on the tip of a high temperature lightpipe or fiber. The ceramic coating replaces conventional sputtered metallic thin films to form a blackbody optical cavity. The ingredients of the composite ceramic material include a mixture of refractory metal oxides forming the bulk of the material, various pigments and/or refractory metal powders, and binding agents. A firing process is used to thermally fuse the coating onto the lightpipe. Embodiments of the firing process include using a flame or furnace technique, or alternatively using various flame- or plasma- spraying techniques.
    Type: Grant
    Filed: April 28, 1992
    Date of Patent: November 15, 1994
    Assignee: Luxtron Corporation
    Inventors: Zhihai Wang, Bruce Adams