Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.

Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.

Abstract: A gate electrode structure of a transistor element may be provided as a series connection of a negative capacitor portion and a floating electrode portion. When forming the negative capacitor portion, the value of the negative capacitance may be adjusted on the basis of two different mechanisms or manufacturing processes, thereby providing superior matching of the positive floating gate electrode portion and the negative capacitor portion. For example, the layer thickness of the ferroelectric material and the effective capacitive area of the dielectric material may be adjusted on the basis of independent manufacturing processes.

Abstract: Circuit structures including a FinFET resonant body transistor are disclosed. One circuit structure includes: a plurality of fins over a substrate and a plurality of gate structures over the plurality of fins, the plurality of gate structures including at least one voltage sensing gate and multiple driving junction gates disposed on opposing sides of the at least one voltage sensing gate; at least one phononic crystal, wherein the at least one phononic crystal is arranged to confine vibrational energy arising from electrically induced mechanical stresses in the fins disposed below the driving junction gates; and, wherein the electrically induced mechanical stresses modulate carrier mobility in the at least one voltage sensing gate to produce a current extractable by the circuit structure.

Abstract: Methods to utilize piezoelectric materials as a gate dielectric in RBTs in an IC device to generate and sense higher frequency signals with high Qs and resulting devices are disclosed. Embodiments include forming, on an upper surface of a semiconductor layer, RBTs comprising even multiples of sensing RBTs and driving RBTs, each RBT including a piezoelectric gate dielectric layer, a gate, and a dielectric spacer on opposite sides of the piezoelectric gate dielectric layer and gate, wherein at least one pair of sensing RBTs is directly between two groups of driving RBTs; forming metal layers, separated by interlayer dielectric layers, above the RBTs; and forming vias through a dielectric layer above the RBTs connecting the RBTs to a metal layer.

Abstract: Circuit structures including a FinFET resonant body transistor are disclosed. One circuit structure includes: a plurality of fins over a substrate and a plurality of gate structures over the plurality of fins, the plurality of gate structures comprising at least one voltage sensing gate, and at least two of the plurality of fins comprising multiple pn-junctions disposed on opposing sides of the at least one voltage sensing gate, the multiple pn-junctions being fabricated to operate as driving units; at least one phononic crystal, wherein the at least one phononic crystal is arranged to confine vibrational energy arising from electrically induced mechanical stresses in the fins comprising driving units; and, wherein the electrically induced mechanical stresses modulate carrier mobility in the at least one voltage sensing gate to produce a current extractable by the circuit structure.

Abstract: Methods to utilize piezoelectric materials as a gate dielectric in RBTs in an IC device to generate and sense higher frequency signals with high Qs and resulting devices are disclosed. Embodiments include forming, on an upper surface of a semiconductor layer, RBTs comprising even multiples of sensing RBTs and driving RBTs, each RBT including a piezoelectric gate dielectric layer, a gate, and a dielectric spacer on opposite sides of the piezoelectric gate dielectric layer and gate, wherein at least one pair of sensing RBTs is directly between two groups of driving RBTs; forming metal layers, separated by interlayer dielectric layers, above the RBTs; and forming vias through a dielectric layer above the RBTs connecting the RBTs to a metal layer.

Abstract: Methods for creating barrier layers in a III-V electron channel to reduce band-to-band leakage current and the resulting devices are disclosed. Embodiments include forming a fin channel portion comprising a III-V material, on a barrier layer; forming undoped InP semiconductor spacers at opposite ends of the fin channel portion on the barrier layer; forming S/D regions adjacent the undoped InP semiconductor spacers on the barrier layer; and forming a high-k/metal gate over the fin channel portion and undoped InP semiconductor spacers.

Abstract: Methods to utilize piezoelectric materials as a gate dielectric in RBTs in an IC device to generate and sense higher frequency signals with high Qs and resulting devices are disclosed. Embodiments include forming, on an upper surface of a semiconductor layer, RBTs comprising even multiples of sensing RBTs and driving RBTs, each RBT including a piezoelectric gate dielectric layer, a gate, and a dielectric spacer on opposite sides of the piezoelectric gate dielectric layer and gate, wherein at least one pair of sensing RBTs is directly between two groups of driving RBTs; forming metal layers, separated by interlayer dielectric layers, above the RBTs; and forming vias through a dielectric layer above the RBTs connecting the RBTs to a metal layer.

Abstract: A semiconductor structure includes a semiconductor substrate, fins coupled to the semiconductor substrate, FinFETs on the fins, a common gate for the FinFETs, a dielectric layer on the semiconductor substrate, the dielectric layer surrounding a cavity with the semiconductor substrate providing bottom confinement of the acoustic cavity by total internal reflection, and an interconnect structure above the FinFETs, the interconnect structure including phononic crystal(s) to confine acoustic energy in the cavity including the cavity and metal layer(s) sandwiched between two dielectric layers. The semiconductor structure may be realized, during FEOL fabrication of a FinFET, by forming a cavity on a surface of a semiconductor substrate. Then, after fabrication of the FinFET, forming an interconnect structure for the FinFET.

Abstract: Approaches for providing asymmetrical channel growth of a cladding layer over fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, in one approach, a FinFET device comprises a set of fins formed from a substrate, a shallow trench isolation layer formed adjacent each of the set of fins, and a cladding layer (e.g., silicon germanium) formed over each of the set of fins, wherein a thickness of the cladding layer atop each of the set of fins is greater than a thickness of the cladding layer along each sidewall of the set of fins. In one embodiment, the thickness of the cladding layer atop the set of fins is approximately two times (2×) greater than the thickness of the cladding layer along each sidewall of the set of fins.

Abstract: One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.

Abstract: One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a graphene liner layer in at least the trench/via, forming a copper-based seed layer on the graphene liner layer, depositing a bulk copper-based material on the copper-based seed layer so as to overfill the trench/via, and performing at least one chemical mechanical polishing process to remove at least excess amounts of the bulk copper-based material and the copper-based seed layer positioned outside of the trench/via to thereby define a copper-based conductive structure with a graphene liner layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract: Methods and apparatus are provided for storing data in a non-volatile memory device. A method includes comparing bits of a write instruction with bits in a memory block to determine bits to be switched in the memory block; determining a switch type for each bit to be switched in the memory block; and evaluating the switch type for each bit to be switched in the memory block. The method further comprises when at least one switch type is a first switch type, performing a first operation on the memory block, and when all of the switch types are not the first switch type, performing a second operation on each bit to be switched in the memory block.

Abstract: One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.

Abstract: Apparatus and related fabrication and read methods are provided for crossbar memory elements. An exemplary crossbar memory element includes a crossbar array structure including a set of access lines, unswitched resistance elements coupled electrically in series between the set of access lines and a reference voltage node, and switched resistance elements coupled electrically in series between the first set of access lines and the reference voltage node. To read from a selected access line, the switched resistance element associated with that access line is enabled while the remaining switched resistance elements are disabled.

Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

Abstract: Methods and apparatus are provided for storing data in a non-volatile memory device. A method includes comparing bits of a write instruction with bits in a memory block to determine bits to be switched in the memory block; determining a switch type for each bit to be switched in the memory block; and evaluating the switch type for each bit to be switched in the memory block. The method further comprises when at least one switch type is a first switch type, performing a first operation on the memory block, and when all of the switch types are not the first switch type, performing a second operation on each bit to be switched in the memory block.

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.