Abstract: Methods are provided for the fabrication of multiple finger transistors. A method comprises forming a layer of gate-forming material overlying a semiconductor substrate and forming a layer of dummy gate material overlying the layer of gate-forming material. The layer of dummy gate material is etched to form a dummy gate and sidewall spacers are formed about sidewalls of the dummy gate. The dummy gate is removed and the layer of gate-forming material is etched using the sidewall spacers as a mask to form at least two gate electrodes.

Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a stack formed over a substrate. The stack includes a gate oxide layer and an overlying polycrystalline silicon layer. The stack further includes first and second undercut regions formed under the polycrystalline silicon layer and adjacent to the gate oxide layer. The memory cell further includes a first charge storage element formed in the first undercut region and a second charge storage element formed in the second undercut region.

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract: A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. An absorption layer is formed on the first layer of dielectric material. The absorption layer includes a plurality of titanium atoms bonded to the first layer of dielectric material, a nitrogen atom bonded to each titanium atom, and at least one ligand bonded to the nitrogen atom. The at least one ligand is removed from the nitrogen atoms to form nucleation centers. A metal such as tungsten is bonded to the nucleation centers to form metallic islands. A dielectric material is formed on the nucleation centers and annealed to form a nanocrystal layer. A control oxide is formed over the nanocrystal layer and a gate electrode is formed on the control oxide.

Abstract: A memory device having a metal nanocrystal charge storage structure and a method for its manufacture. The memory device may be manufactured by forming a first oxide layer on the semiconductor substrate, then disposing a porous dielectric layer on the oxide layer and disposing a second oxide layer on the porous dielectric layer. A layer of electrically conductive material is formed on the second layer of dielectric material. An etch mask is formed on the electrically conductive material. The electrically conductive material and the underlying dielectric layers are anisotropically etched to form a dielectric structure on which a gate electrode is disposed. A metal layer is formed on the dielectric structure and the gate electrode and treated so that portions of the metal layer diffuse into the porous dielectric layer. Then the metal layer is removed.

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract: A method for doping fin structures in FinFET devices includes forming a first glass layer on the fin structure of a first area and a second area. The method further includes removing the first glass layer from the second area, forming a second glass layer on the fin structure of the first area and the second area, and annealing the first area and the second area to dope the fin structures.

Abstract: A fully depleted SOI MOSFET arrangement includes a buried oxide (BOX) layer with recesses in the BOX layer and a post extended upwardly between the recesses. A thin channel region is formed on the post and a gate over the channel. Deep source/drain region are adjacent to the channel region and extend into the recesses.

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin, an oxide layer, spacers and one or more control gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The oxide layer is formed on the fin and acts as a tunnel oxide for the memory device. The spacers are formed adjacent the side surfaces of the fin and the control gates are formed adjacent the spacers. The spacers act as floating gate electrodes for the non-volatile memory device.

Abstract: A method and system for providing a halo implant to a semiconductor device is disclosed. The method and system includes providing a thin photoresist layer that covers a substantial amount of an active area including a source region and a drain region of the semiconductor device. The method and system further includes providing the halo implant to the semiconductor device, using the thin photoresist layer as a mask. Utilizing this thin photoresist layer, taking into account other height variables, the source and drain regions can be opened only as needed. At a 45° angle, the implant can be delivered to all transistors in the circuit in the targeted area as well as getting only a large amount of the dose (up to ¾ of the dose) to the transistor edge which sits on the trench edge.

Abstract: A method of forming a semiconductor device includes forming a fin on an insulating layer, where the fin includes a number of side surfaces, a top surface and a bottom surface. The method also includes forming a gate on the insulating layer, where the gate has a substantially U-shaped cross-section at a channel region of the semiconductor device.

Abstract: A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side. A triple gate MOSFET includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, a second gate formed adjacent a second side of the germanium fin opposite the first side, and a top gate formed on top of the germanium fin. An all-around gate MOSFET includes a germanium fin, a first sidewall gate structure formed adjacent a first side of the germanium fin, a second sidewall gate structure formed adjacent a second side of the germanium fin, and additional gate structures formed on and around the germanium fin.

Abstract: A semiconductor device with a superlattice and method of making same includes forming a layer of amorphous silicon over a substrate, and forming a layer of nanocrystals by laser thermal annealing the layer of amorphous silicon. A gate dielectric is formed between the layer of amorphous silicon and the substrate. A dielectric layer is formed on the layer of amorphous silicon. The steps of forming the layer of amorphous silicon and forming the dielectric layer can be repeated. The thickness of the dielectric layer is between about 25 to 40 angstroms, and the thickness of the amorphous silicon layer is between about 30 to 50 angstroms. The average diameter of the nanocrystals is less than 40 angstroms.

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract: A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.

Abstract: A non-volatile memory device is provided by forming a tunnel oxide layer and a gate electrode on the tunnel oxide layer. Silicon structures are formed below the side surfaces of the gate electrode and act as a floating gate electrode for the non-volatile memory device.

Abstract: A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

Abstract: A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.

Abstract: A method for forming a FDSOI device with channel length less than 50 nm with good short channel control. The gate has a tapered polysilicon spacer and a dielectric spacer. A polysilicon gate feature is formed and dielectric sidewall spacers are formed thereon. The polysilicon gate feature is then etched to form tapered poly features separated by a gap. A gate dielectric is deposited at low temperature, then metal is deposited into the gap to form the metal gate.

Abstract: A narrow channel FinFET is described herein with a narrow channel width. A protective layer may be formed over the narrow channel, the protective layer being wider than the narrow channel.