Patents by Inventor Zoran Krivokapic
Zoran Krivokapic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8431466Abstract: A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure.Type: GrantFiled: July 5, 2011Date of Patent: April 30, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Ming-ren Lin, Zoran Krivokapic, Witek Maszara
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Patent number: 8368219Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.Type: GrantFiled: October 26, 2011Date of Patent: February 5, 2013Assignees: Advanced Micro Devices, Inc., Spansion LLCInventors: Arvind Halliyal, Zoran Krivokapic, Matthew S. Buynoski, Nicholas H. Tripsas, Minh Van Ngo, Mark T. Ramsbey, Jeffrey A. Shields, Jusuke Ogura
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Patent number: 8334181Abstract: A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side. A triple gate MOSFET includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, a second gate formed adjacent a second side of the germanium fin opposite the first side, and a top gate formed on top of the germanium fin. An all-around gate MOSFET includes a germanium fin, a first sidewall gate structure formed adjacent a first side of the germanium fin, a second sidewall gate structure formed adjacent a second side of the germanium fin, and additional gate structures formed on and around the germanium fin.Type: GrantFiled: July 14, 2010Date of Patent: December 18, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Judy Xilin An, Zoran Krivokapic, Haihong Wang, Bin Yu
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Patent number: 8331135Abstract: A chain of field coupled nanomagnets includes at least one elements having substantially different anisotropy energy from that of the other nanomagnets. A signal can propagate from a first input nanomagnet having a relatively high anisotropy energy through the chain to an output nanomagnet. The output nanomagnet may have a relatively lower anisotropy energy than the other nanomagnets. Signal flow direction thus can be controlled. The higher anisotropy energy nanomagnet may be attained by use of a ferromagnet material having a higher anisotropy constant and/or configured with a larger volume than the other elements. The lower anisotropy energy magnet may be attained by use of a ferromagnet material having a lower anisotropy constant and/or configured with a smaller volume than the other elements. Logic signal flow control can also be attained making use of three dimensional geometries of nanomagnets with two different orientations.Type: GrantFiled: December 22, 2009Date of Patent: December 11, 2012Assignee: Globalfoundries Inc.Inventors: An Chen, Zoran Krivokapic
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Patent number: 8304760Abstract: A device is provided that includes a structure having a sidewall surface, a layer of material provided on the sidewall surface, and a device structure provided in contact with the layer of material. Fabrication techniques includes a process that includes forming a structure having a sidewall surface, forming a layer of material on the sidewall surface, and forming a device structure in contact with the layer of material, where the device structure and the layer of material are components of a device.Type: GrantFiled: June 13, 2011Date of Patent: November 6, 2012Assignee: Advanced Micro Devices, Inc.Inventors: An Chen, Zoran Krivokapic
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Publication number: 20120252193Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.Type: ApplicationFiled: June 14, 2012Publication date: October 4, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Ming-Ren LIN, Judy Xilin AN, Zoran KRIVOKAPIC, Cyrus E. TABERY, Haihong WANG, Bin YU
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Patent number: 8222680Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.Type: GrantFiled: October 22, 2002Date of Patent: July 17, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Ming-Ren Lin, Judy Xilin An, Zoran Krivokapic, Cyrus E. Tabery, Haihong Wang, Bin Yu
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Patent number: 8207757Abstract: Apparatus and related fabrication and operating methods are provided for logic circuits that include ferromagnetic elements. An exemplary logic circuit includes a first ferromagnetic element having a first ferromagnetic layer, a second ferromagnetic element having a second ferromagnetic layer, and a transistor coupled to the first ferromagnetic element. The first transistor is configured to allow current to flow through the first ferromagnetic element. The current influences the magnetization direction of the first ferromagnetic layer, which, in turn, influences the magnetization direction of the second ferromagnetic layer.Type: GrantFiled: February 7, 2011Date of Patent: June 26, 2012Assignee: Globalfoundries, Inc.Inventors: An Chen, Zoran Krivokapic
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Publication number: 20120081944Abstract: Apparatus and related fabrication and read methods are provided for crossbar memory elements. An exemplary crossbar memory element includes a crossbar array structure including a set of access lines, unswitched resistance elements coupled electrically in series between the set of access lines and a reference voltage node, and switched resistance elements coupled electrically in series between the first set of access lines and the reference voltage node. To read from a selected access line, the switched resistance element associated with that access line is enabled while the remaining switched resistance elements are disabled.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: An CHEN, Zoran KRIVOKAPIC
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Publication number: 20120038051Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.Type: ApplicationFiled: October 26, 2011Publication date: February 16, 2012Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Arvind Halliyal, Zoran Krivokapic, Matthew S. Buynoski, Nicholas H. Tripsas, Minh Van Ngo, Mark T. Ramsbey, Jeffery A. Shields, Jusuke Ogura
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Patent number: 8102000Abstract: According to one exemplary embodiment, a p-channel germanium on insulator (GOI) one transistor memory cell comprises a buried oxide (BOX) layer formed over a bulk substrate, and a gate formed over a gate dielectric layer situated over a germanium layer formed over the buried oxide (BOX) layer. A source region is formed in the germanium layer adjacent to a channel region underlying the gate and overlaying the BOX layer, and a drain region is formed in the germanium layer adjacent to the channel region. The source region and the drain region are implanted with a p-type dopant. In one embodiment, a p-channel GOI one transistor memory cell is implemented as a capacitorless dynamic random access memory (DRAM) cell. In one embodiment, a plurality of p-channel GOI one transistor memory cells are included in a memory array.Type: GrantFiled: April 10, 2008Date of Patent: January 24, 2012Assignee: GLOBALFOUNDRIES Inc.Inventor: Zoran Krivokapic
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Patent number: 8049334Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.Type: GrantFiled: July 26, 2010Date of Patent: November 1, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Arvind Halliyal, Zoran Krivokapic, Matthew S. Buynoski, Nicholas H. Tripsas, Minh Van Ngo, Mark T. Ramsbey, Jeffrey A. Shields, Jusuke Ogura
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Publication number: 20110263094Abstract: A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure.Type: ApplicationFiled: July 5, 2011Publication date: October 27, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Ming-ren LIN, Zoran KRIVOKAPIC, Witek MASZARA
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Publication number: 20110253983Abstract: A device is provided that includes a structure having a sidewall surface, a layer of material provided on the sidewall surface, and a device structure provided in contact with the layer of material. Fabrication techniques includes a process that includes forming a structure having a sidewall surface, forming a layer of material on the sidewall surface, and forming a device structure in contact with the layer of material, where the device structure and the layer of material are components of a device.Type: ApplicationFiled: June 13, 2011Publication date: October 20, 2011Applicant: Advanced Micro Devices, Inc.Inventors: An Chen, Zoran Krivokapic
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Patent number: 7994020Abstract: A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure.Type: GrantFiled: July 21, 2008Date of Patent: August 9, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Ming-ren Lin, Zoran Krivokapic, Witek Maszara
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Patent number: 7993986Abstract: A device is provided that includes a structure having a sidewall surface, a layer of material provided on the sidewall surface, and a device structure provided in contact with the layer of material. Fabrication techniques includes a process that includes forming a structure having a sidewall surface, forming a layer of material on the sidewall surface, and forming a device structure in contact with the layer of material, where the device structure and the layer of material are components of a device.Type: GrantFiled: August 29, 2008Date of Patent: August 9, 2011Assignee: Advanced Micro Devices, Inc.Inventors: An Chen, Zoran Krivokapic
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Patent number: 7973364Abstract: According to one exemplary embodiment, a method for fabricating a one-transistor memory cell includes forming an opening by removing a portion of a gate stack of a silicon-on-insulator (SOI) device, where the SOI device is situated over a buried oxide layer. The method further includes forming a bottom gate of the one-transistor memory cell in a bulk substrate underlying the buried oxide layer. The method further includes forming a charge trapping region in the buried oxide layer. The charge trapping region is formed at an interface between a silicon layer underlying the gate stack and the buried oxide layer. The charge trapping region causes the one-transistor memory cell to have an increased sensing margin. The method further includes forming a top gate of the one-transistor memory cell in the opening. Also disclosed is an exemplary one-transistor memory cell fabricated utilizing the exemplary disclosed method.Type: GrantFiled: February 27, 2008Date of Patent: July 5, 2011Assignee: GLOBALFOUNDRIES Inc.Inventor: Zoran Krivokapic
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Publication number: 20110147709Abstract: A chain of field coupled nanomagnets includes at least one elements having substantially different anisotropy energy from that of the other nanomagnets. A signal can propagate from a first input nanomagnet having a relatively high anisotropy energy through the chain to an output nanomagnet. The output nanomagnet may have a relatively lower anisotropy energy than the other nanomagnets. Signal flow direction thus can be controlled. The higher anisotropy energy nanomagnet may be attained by use of a ferromagnet material having a higher anisotropy constant and/or configured with a larger volume than the other elements. The lower anisotropy energy magnet may be attained by use of a ferromagnet material having a lower anisotropy constant and/or configured with a smaller volume than the other elements. Logic signal flow control can also be attained making use of three dimensional geometries of nanomagnets with two different orientations.Type: ApplicationFiled: December 22, 2009Publication date: June 23, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: An Chen, Zoran Krivokapic
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Patent number: 7939247Abstract: A process is provided that includes forming a first mask on an underlying layer, where the mask has two adjacent portions with an open gap therebetween, and depositing a second mask material within the open gap and at an inclined angle with respect to an upper surface of the underlying layer to form a second mask. In another implementation, a process is provided that includes forming a first mask on an underlying layer, where the mask has a pattern that includes an open gap, and depositing a second mask material within the open gap to form a second mask, where particles of the second mask material are directed in parallel or substantially in parallel to a line at an inclined angle with respect to an upper surface of the underlying layer.Type: GrantFiled: August 29, 2008Date of Patent: May 10, 2011Assignee: Globalfoundries Inc.Inventors: An Chen, Zoran Krivokapic
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Patent number: 7871873Abstract: A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.Type: GrantFiled: March 27, 2009Date of Patent: January 18, 2011Assignee: GLOBAL FOUNDRIES Inc.Inventors: Witold Maszara, Ming-Ren Lin, Jin Cho, Zoran Krivokapic