Methods of fabricating integrated circuit chips for multi-chip packaging and wafers and chips formed thereby
Methods of forming integrated circuit chips include forming a plurality of criss-crossing grooves in a semiconductor wafer having a plurality of contact pads thereon and filling the criss-crossing grooves with an electrically insulating layer. The electrically insulating layer is then patterned to define at least first and second through-holes therein that extend in a first one of the criss-crossing groves. The first and second through-holes are then filled with first and second through-chip connection electrodes, respectively. The semiconductor wafer is then diced into a plurality of integrated circuit chips by cutting through the electrically insulating layer in a criss-crossing pattern that overlaps with the locations of the criss-crossing grooves.
This application claims priority to Korean Application Serial No. 2004-58689, filed Jul. 23, 2004, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTIONThe present invention relates to methods of fabricating integrated circuit chips and, more particularly, to methods of fabricating integrated circuit chips suitable for multi-chip packaging.
BACKGROUND OF THE INVENTIONMulti-chip package (MCP) technologies typically include methods of fabricating integrated circuit chips that may be combined side-by-side or stacked together within a single integrated circuit package or module. The use of MCP technologies can significantly increase the integration density of integrated circuits, including those that are used in hand-held and other small devices (e.g., cellular phones). An example of an MCP technology that uses wiring plugs within penetrant apertures that extent through an integrated circuit chip is disclosed in U.S. Pat. No. 6,429,096 to Yanagida. These wiring plugs support the electrical interconnection of a plurality of chips that can be stacked vertically within a single integrated circuit package. Another example of an MCP technology that uses through-holes is disclosed in U.S. Pat. No. 6,566,232 to Hara et al.
Other packaging technologies that seek to increase the integration densities of integrated circuit chips on a substrate (e.g., printed circuit board (PCB)) include chip scale packaging (CSP) technologies. These CSP technologies seek to increase integration levels using packages that have very small form factors and are nearly the same size as the integrated circuit chip(s) they enclose. One commonly accepted requirement of a CSP package requires that it have a lateral footprint that is no greater than about 1.2 times the size of the semiconductor chip it encloses. An example of a CSP packaging technology is disclosed in U.S. Pat. No. 6,774,475 to Blackshear et al. One type of CSP technology includes wafer-level chip-scale packaging (WLCSP), which enables an integrated circuit chip to be mounted face-down to a printed circuit board (PCB), with the chip's pads connected to the board's pads through individual solder balls without needing any underfill material. This technology differ from other ball-grid array (BGA) technologies because there is typically no bond wires or interposer connections. The principle advantage of WLCSP is that the IC-to-PC board inductance is minimized and the secondary advantages are the reduction in package size and manufacturing cycle time and the enhanced thermal conduction characteristics. Another type of CSP technology, which describes initially forming partial through-holes in a semiconductor substrate and then removing an underside surface of the substrate to expose the through-holes, is disclosed in Korean Laid Open Patent Application No. 2003-0023040.
Similarly, the second chip 10b is illustrated as including a second semiconductor substrate 12b having a second through-hole 17b therein. The second through-hole 17b extends from an upper surface of the substrate 12b to a lower surface of the substrate 12b. A second passivation layer 13b is provided on the upper surface of the substrate 12b. This second passivation layer 13b has an opening therein that exposes a second chip pad 11b. A second insulating layer 18b is also provided. This second insulating layer 18b extends on the second passivation layer 13b and directly on sidewalls of the second through-hole 17b. A second metal layer 21b is provided directly on the second chip pad 11b. This second metal layer 21b also extends on the second insulating layer 18b and into the second through-hole 17b. The second through-hole 17b is filled by a second electrode metal layer 22b, which is electrically coupled to the second chip pad 11b by the second metal layer 21b.
An electrical interconnection is provided between the first and second integrated circuit chips 10a and 10b and the first and second chip pads 11a and 11b. This electrical interconnection is provided by a first metal bump 24a (e.g., solder ball), which electrically connects the first electrode metal layer 22a to the second electrode metal layer 22b. A second metal bump 24b is also provided to electrically connect the second electrode metal layer 22b to an underlying chip, package or printed circuit board (not shown).
As will be understood by those skilled in the art, the first and second integrated circuit chips 10a and 10b may be formed from a common semiconductor wafer (not shown) containing integrated circuits therein and a plurality of chip pads thereon, which are partially covered by a passivation layer (shown as 13a and 13b in
Unfortunately, the conventional fabrication step of laser drilling to form through-holes in a semiconductor wafer is a relatively lengthy process step that may require each hole to be formed one-at-a-time in sequence. Moreover, the drilling of holes may damage the semiconductor wafer and result in through-holes with tapered sidewall profiles. The formation of tapered sidewall profiles may lead to the formation of electrode metal layers that are susceptible to defects (e.g., electrical disconnection). Thus, notwithstanding these conventional techniques for forming integrated circuit chips that may be stacked together to provide high levels of integration, there continues to be a need for improved methods of forming through-holes in semiconductor wafers and chips.
SUMMARY OF THE INVENTIONSemiconductor chips according to embodiments of the present invention use outer edge insulating layers with through-holes therein that provide reliable interconnection vias when the chips are used in stacked multi-chip packaging applications. In some of these embodiments, a semiconductor substrate is provided having upper and lower faces thereon that extend to an outer edge thereof. At least a first contact pad is provided on a portion of the upper face extending adjacent the outer edge. An electrically insulating region is provided on the outer edge of the semiconductor substrate. This electrically insulating region, which may surround an entire periphery of the semiconductor substrate, includes at least one through-hole that extends vertically through an entire thickness of the electrically insulating region and has a longitudinal axis that is substantially parallel to the outer edge of the semiconductor substrate. A connection electrode is also provided. This connection electrode extends through the through-hole and is electrically connected to the first contact pad. The electrically insulating layer may have a lower surface that is coplanar with the lower face of the semiconductor substrate and an upper surface that is above the upper face of the semiconductor substrate, which results in a length of the through-hole being greater than a thickness of the semiconductor substrate. In particular, the electrically insulating layer may wrap around the outer edge and extend onto a passivation layer covering the semiconductor substrate.
Additional embodiments of the invention include a semiconductor chip having a peripheral edge defined by an electrically insulating region having interconnect through-holes therein. The semiconductor chip includes a semiconductor substrate having upper and lower faces thereon that extend to an outer edge thereof. An electrically insulating region is provided on the outer edge of the semiconductor substrate. The electrically insulating region has a through-hole therein that is filled within a connection electrode. A solder bump is also provided. The solder bump is electrically connected to a portion of the connection electrode extending adjacent a bottom of the through-hole.
Still further embodiments of the invention include methods of fabricating a plurality of integrated circuit chips from a semiconductor wafer. These methods include forming a plurality of crisscrossing grooves in a semiconductor wafer having a plurality of contact pads thereon. The criss-crossing grooves are then filled with an electrically insulating layer. The electrically insulating layer is patterned to define at least first and second through-holes therein, which extend into a first one of the criss-crossing groves. The first and second through-holes are filled with first and second through-chip connection electrodes, respectively. The semiconductor wafer is then diced into a plurality of integrated circuit chips. This dicing step may be performed by cutting through the electrically insulating layer in a criss-crossing pattern that overlaps with the locations of the crisscrossing grooves.
In additional embodiments of the invention, the dicing step is preceded by the step of removing an underside of the semiconductor wafer to thereby expose the first and second through-chip connection electrodes and the electrically insulating layer. The step of filling the first and second through-holes may also include depositing a base metal layer that extends on the electrically insulating layer and lines the first and second through-holes and then electroplating the first and second through-chip connection electrodes into the first and second through-holes using the base metal layer as an electroplating electrode. The base metal layer may then be etched back using the first and second through-chip connection electrodes as an etching mask.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention now will be described more fully herein with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity of description. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like elements throughout.
Methods of forming integrated circuit chips according to embodiments of the present invention will now be described with reference to
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After the through-holes 41 have been formed, a blanket base metal layer 42 may be deposited on the wafer 30. As illustrated by
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In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Claims
1. A semiconductor chip, comprising:
- a semiconductor substrate having upper and lower faces thereon that extend to an outer edge thereof and at least a first contact pad on a portion of the upper face extending adjacent the outer edge;
- an electrically insulating region on the outer edge of said semiconductor substrate, said electrically insulating region having through-hole therein; and
- a connection electrode that extends through said through-hole and is electrically connected to the first contact pad.
2. The semiconductor chip of claim 1, wherein said electrically insulating layer has a lower surface that is coplanar with the lower face of said semiconductor substrate.
3. The semiconductor chip of claim 1, wherein a length of the through-hole is greater than a thickness of said semiconductor substrate.
4. The semiconductor chip of claim 3, wherein a longitudinal axis of the through-hole is substantially parallel to the outer edge of said semiconductor substrate.
5. The semiconductor chip of claim 1, further comprising a passivation layer extending on the upper face and having an opening therein that exposes the first contact pad; and wherein said electrically insulating region wraps around the outer edge and extends onto the passivation layer.
6. The semiconductor chip of claim 5, wherein said electrically insulating region extends between the upper face and said connection electrode.
7. The semiconductor chip of claim 1, wherein an outer edge of said electrically insulating region represents an outer edge of the semiconductor chip.
8. A semiconductor chip, comprising:
- a semiconductor substrate having upper and lower faces thereon that extend to an outer edge thereof;
- an electrically insulating region on the outer edge of said semiconductor substrate, said electrically insulating region having through-hole therein with a length greater than a thickness of said semiconductor substrate;
- a connection electrode extending through the through-hole; and
- a solder bump electrically connected to a portion of said connection electrode extending adjacent a bottom of the through-hole.
9. The semiconductor chip of claim 8, wherein an outer edge of said electrically insulating region represents an outer edge of the semiconductor chip.
10. A method of fabricating a plurality of integrated circuit chips, comprising the steps of:
- forming a plurality of criss-crossing grooves in a semiconductor wafer having a plurality of contact pads thereon;
- filling the crisscrossing grooves with an electrically insulating layer;
- patterning the electrically insulating layer to define at least first and second through-holes therein that extend in a first one of the criss-crossing groves;
- filling the first and second through-holes with first and second through-chip connection electrodes, respectively; and
- dicing the semiconductor wafer into a plurality of integrated circuit chips by cutting through the electrically insulating layer in a crisscrossing pattern that overlaps with the locations of the criss-crossing grooves.
11. The method of claim 10, wherein said dicing step is preceded by the step of removing an underside of said semiconductor wafer to thereby expose the first and second through-chip connection electrodes and the electrically insulating layer.
12. The method of claim 11, wherein said step of filling the first and second through-holes comprises the steps of:
- depositing a base metal layer that extends on the electrically insulating layer and lines the first and second through-holes;
- electroplating the first and second through-chip connection electrodes into the first and second through-holes; and
- etching back the base metal layer using the first and second through-chip connection electrodes as an etching mask.
13. The method of claim 10, wherein said step of filling the first and second through-holes comprises the steps of:
- depositing a base metal layer that extends on the electrically insulating layer and lines the first and second through-holes;
- electroplating the first and second through-chip connection electrodes into the first and second through-holes; and
- etching back the base metal layer using the first and second through-chip connection electrodes as an etching mask.
14. The method of claim 13, wherein said electroplating step comprises electroplating the first and second through-chip connection electrodes into the first and second through-holes using the base metal layer as an electroplating electrode.
15. The method of claim 14, wherein said electroplating step is preceded by the step of patterning an electroplating mask on the base metal layer.
16. A method of fabricating an integrated circuit chip, comprising the steps of:
- forming a groove in a semiconductor substrate;
- filling the groove with an electrically insulating region;
- forming first and second through-holes in the electrically insulating region;
- filling the first and second through-holes with first and second connection electrodes, respectively;
- removing an underside of the semiconductor substrate to thereby expose the electrically insulating region and the first and second connection electrodes; and
- dicing the semiconductor substrate into first and second semiconductor chips by cutting through the electrically insulating region at a location extending between the first and second connection electrodes.
17. The method of claim 16, wherein said step of filling the first and second through-holes comprises electroplating first and second connection electrodes into the first and second through-holes.
18. A method of processing a semiconductor wafer, comprising the steps of:
- forming a plurality of criss-crossing grooves in a semiconductor wafer;
- filling the criss-crossing grooves with an electrically insulating layer;
- removing an underside of the semiconductor wafer to thereby expose a surface of the electrically insulating layer having a criss-crossing pattern; and
- dicing the semiconductor wafer into a plurality of integrated circuit chips having electrically insulating edges by cutting through the electrically insulating region at locations defined by the criss-crossing pattern.
19. The method of claim 18, wherein said removing step is preceded by the steps of:
- forming a plurality of through-holes in the electrically insulating layer; and
- filling the plurality of through-holes with a corresponding plurality of connection electrodes.
20. The method of claim 19, wherein said removing step comprises removing an underside of the semiconductor wafer to thereby expose a surface of the electrically insulating layer and the plurality of connection electrodes.
Type: Application
Filed: Jun 8, 2005
Publication Date: Jan 26, 2006
Inventors: In-Young Lee (Gyeonggi-do), Sung-Min Sim (Gyeonggi-do), Dong-Hyeon Jang (Gyeonggi-do), Hyun-Soo Chung (Gyeonggi-do), Young-Hee Song (Gyeonggi-do), Myeong-Soon Park (Gyeonggi-do)
Application Number: 11/147,677
International Classification: H01L 21/78 (20060101);