POWER SEMICONDUCTOR PACKAGE
The present invention features a power semiconductor package and a method of forming the same that includes forming, in the body, a stress relief region disposed between a pair of mounting regions and attaching a semiconductor die in each of the mounting regions. The semiconductor die has first and second sets of electrical contacts with the first set being on a first surface of the semiconductor die and the second set being disposed upon a second surface of the semiconductor die opposite to the first surface. The first set is in electrical communication with the mounting region. Walls are formed on outer sides of the pair of mounting regions, defining a shaped body, with the shaped body and walls defining an electrically conductive path that extends from the first set and terminates on side of the package common with the second set.
The present invention generally relates to semiconductor packages and more particularly to power semiconductor packages and methods of making power semiconductor packages.
Optimizing the operational performance of power semiconductor packages requires satisfaction of several constraints. The constraints include acceptable power density, parasitics, reliability and cost of manufacture. Power density is related to heat dissipation of the package. As a result, obtaining desired power density often requires efficient cooling of the package. One manner in which to achieve cooling of the package is by exposing thermally conductive features, such as metal and silicon, of the active components of the package to an ambient environment. It is typically desired to configure the package to provide mechanical protection to the silicon features.
Elimination of wire bonds facilitates obtaining acceptable parasitics (e.g., parasitic resistance and inductance). To that end, interconnection of the active components is often facilitated by clip bonding, chip-only ball grid array with solder balls/bumps. The drawback of clip bonding is that the top exposure area is limited and a traditional mold process is required for package integrity. The drawback of chip-only ball grid array is that the connection to certain active components, such as the drain of a bottom-drain vertical MOSFET, is problematic. The mechanical integrity of the ball grid array may become compromised when operating at the upper power limits of the package. In addition, the semiconductor chip may be exposed to physical damage in such a configuration. The process of mounting a semiconductor chip, or a package with multiple chips may also experience stresses from the different coefficients of thermal expansion.
Cost of manufacture may be controlled by minimizing the amount of materials employed to fabricate the same. This may be achieved by obtaining, as close as possible, the ratio of the size of the package to the size of the active element to be 1:1. Also, the miniaturization of parts is an ongoing goal in the field of electronics. Reducing the complexity of the process by which to fabricate the package may also reduce cost.
Reliability may be provided by ensuring the mechanical strength of the package. To that end, it would be desired to provide physical protection to the semiconductor silicon of the active elements, while improving the robustness of the package.
A need exists, therefore, to provide power semiconductor packages having desired operational characteristics.
SUMMARY OF THE INVENTIONThe present invention features a power semiconductor package and a method of forming the same that includes forming, in the body, a stress relief region disposed between a pair of mounting regions and attaching a semiconductor die in each of the mounting regions. The semiconductor die has first and second sets of electrical contacts with the first set being disposed on a first surface of the semiconductor die and the second set being disposed upon a second surface of the semiconductor die opposite to the first surface. The first set is in electrical communication with the mounting region. Walls are formed on outer sides of the pair of mounting regions, defining a shaped body, with the shaped body and walls defining an electrically conductive path that extends from the first set and terminates on a side of the package common with the second set. The stress relief region is configured to create differential rigidity between the stress relief region and the remaining portions of the body such that the remaining portions have a greater stiffness associated therewith than the stress relief region. To that end, the stress relief region may be formed from a plurality of apertures in the stamped body, or a bend in the stamped body that extends along the entire length thereof or a combination thereof. Typically, one or more semiconductor dies are fixedly attached to the mounting regions. Optionally, an additional semiconductor chip, e.g., a controller integrated circuit (IC) chip, my be stacked on the one or more semiconductor dies. To provide mechanical protection to the semiconductor dies, the stamped body includes opposed walls, with each of the pair of mounting regions extending from the wall and terminating proximate to the stress relief region. These and other aspects of the invention are discussed more fully below.
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Mechanical protection is provided to semiconductor dies 40 and 42 by fabricating body 12 from a mechanically robust material, compared to the semiconductor material from which semiconductor dies 40 and 42 are fabricated. For example, body 12 may be formed from metal and provided with a sufficient thickness to resist damage. Semiconductor dies 40 and 42 often include metallic contacts 60-67. Contacts 60-63 are mounted to die surface 68 of semiconductor die 40, and contacts 64-67 are mounted to die surface 70 of semiconductor die 42. Additionally, walls 20 and 22 are dimensioned to form a protective cavity, within package 10, for semiconductor dies 40 and 42. To that end, wall 20 extends from mounting surface 16 ending in a lead region 72, and wall 22 extends from surface 18 ending in a lead region 74. Lead region 72 and lead region 74 each have a surface 76 and 78, respectively, that lie in a common plane 80. Additional mechanical strength is provided to wall 20 by the presence of a bulwark disposed at a terminus thereof opposite to lead region 72, which defines a shoulder 82. Similarly, wall 22 includes a bulwark that defines shoulder 84. These shoulders may be formed by a half-etch process of the body 12. To control a thickness 86 of package 10, the bend in stress relief region 14 is established to form juncture 48 that is spaced-apart from both planes 50 and 80.
Package 10 may be mounted onto a surface such as a printed circuit board (PCB) 99 which lies in plane 80, as shown in
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It should be understood that the foregoing description is merely an example of the invention and that modifications and may be made thereto without departing from the spirit and scope of the invention and should not be construed as limiting the scope of the invention. For example, the mounting regions may include multiple layers of material to provide desired electrical characteristics to the mounting surface. An electrically insulating layer may be deposited over the mounting surface with an electrical conductive layer being disposed over the electrically insulating layer. Semiconductor dies may then be fixedly attached to the electrically insulating layer, using known techniques. The scope of the invention, therefore, should be determined with respect to the appended claims, including the full scope of equivalents thereof.
Claims
1. A method of forming a power semiconductor package from a body, said method comprising:
- forming, in said body, a stress relief region disposed between a pair of mounting regions;
- attaching a semiconductor die in each of said mounting regions, said semiconductor die having first and second sets of electrical contacts with said first set being on a first surface of said semiconductor die and said second set being disposed upon a second surface of said semiconductor die opposite to said first surface, with said first set being in electrical communication with said mounting region; and
- forming walls on outer sides of said pair of mounting regions, defining a shaped body, with said shaped body and walls defining an electrically conductive path that extends from said first set and terminates on a side of said package common with said second set.
2. The method as recited in claim 1 wherein forming a stress relief region and forming said walls further comprises providing a relatively flat body and stamping it into said shaped body.
3. The method as recited in claim 2 further comprising before stamping, half etching said flat body to form recessed portions for mounting regions.
4. The method as recited in claim 1 wherein said shaped body is made of metal.
5. The method as recited in claim 2 wherein stamping further includes providing features in a portion of said body to create a differential rigidity between said stress relief region and remaining portions of said body such that the remaining portions have a greater stiffness associated therewith than said stress relief regions.
6. The method as recited in claim 2 wherein stamping further includes forming a plurality of apertures in said stress relief region.
7. The method as recited in claim 2 wherein stamping further includes forming a bend in said stress relief region that extends along the length thereof.
8. The method as recited in claim 2 wherein stamping further includes forming a plurality of apertures in said stress relief region and a bend extending the length of said stress relief region.
9. The method as recited in claim 1 further including attaching solder balls to a side of said plurality of semiconductor dies facing away from said mounting regions.
10. The method as recited in claim 1 further comprising attaching a passive electrical element to said mounting regions.
11. The method as recited in claim 1 further including fixedly mounting to said second surface of said semiconductor die in each of said mounting regions, an additional die in superimposition with a portion of said second surface.
12. The method as recited in claim 11 wherein said semiconductor die is a field effect transistor (FET), and wherein said additional die comprises an integrated circuit (IC) control chip, said IC control chip being used to control said FET.
13. The method as recited in claim 12 further comprising attaching an inductor onto the said mounting regions.
14. The method as recited in claim 1 wherein forming walls further comprises forming walls such that the ends terminate coplanar to electrical connections from said second set of electrical contacts.
15. A semiconductor power package, comprising:
- a shaped body having a stress relief region disposed between a pair of mounting regions and opposed walls, with each of said mounting regions extending from one of said opposed walls and terminating proximate to said stress relief region, and having a mounting surface, with each of said pair of opposed walls extending from said mounting surface and terminating in a lead portion, said lead portion extending transversely to said opposed walls, said stress relief region having a stiffness associated therewith that is less than the stiffness of the remaining portions of said body; and
- a plurality of semiconductor dies, each of which is attached to one of said pair of mounting regions and in superimposition with said mounting surface and includes first and second sets of electrical contacts, with said first set being on a first surface of said semiconductor die and said second set being disposed upon a second surface of said semiconductor die opposite to said first surface, with said first set being in electrical communication with said mounting surface, said shaped body defining an electrically conductive path that extends from said first set and terminates on a side of said package common with said second set.
16. The package as recited in 15 wherein said shaped body is made of metal.
17. The package as recited in claim 15 wherein said stress relief region further includes a plurality of spaced-apart apertures formed in said body.
18. The package as recited in claim 15 wherein said stress relief region further includes a bend formed into said body along entire length of said stress relief region.
19. The package as recited in claim 15 wherein said stress relief region further includes a plurality of spaced-apart apertures formed in said body and a bend formed into said body along entire length of said stress relief region.
20. The package as recited in claim 15 wherein said lead portions of the walls are coplanar to electrical connections from said second set of electrical contacts.
21. The package as recited in claim 15 further including an additional semiconductor die attached to said plurality of semiconductor dies, with said additional semiconductor die having electrodes disposed upon a side thereof facing away from said plurality of semiconductor dies.
22. The package as recited in claim 21 wherein said additional semiconductor die is an integrated circuit (IC) control chip, and at least one of said plurality of semiconductor dies is a field effect transistor (FET).
23. The package as recited in claim 15 further including an additional semiconductor die attached to said plurality of semiconductor dies, with said additional semiconductor die having electrodes disposed upon a side thereof facing away from said plurality of semiconductor dies, with a portion of each of said plurality of semiconductor dies being in superimposition with said additional semiconductor die with a plurality of solder balls being attached to said plurality of semiconductor dies in areas thereof outside of said portion.
24. The package as recited in claim 15 further including an additional semiconductor die attached to plurality of semiconductor dies, defining a die stack, with said additional semiconductor die having electrodes disposed upon a side thereof facing away from said plurality of semiconductor dies, and a passive element mounted on said pair of mounting regions and disposed adjacent to said die stack.
25. The package as recited in claim 24 wherein said passive element is an inductor.
26. A metal body for a semiconductor power package comprising:
- two planar central sections for semiconductor die attachment;
- two wall portions extending down from opposite ends of the central section; and
- a stress relief portion disposed between the planar central section parallel to said two wall portions, said stress relief portion being flexible in comparison to the planar central section.
27. The metal body of claim 26 wherein said walls form a cavity for a semiconductor die to be attached onto the central section and sized such that upon attaching a side of a semiconductor die to said central section, and opposing side aid of said semiconductor die would be electrically connected ends of said walls, with said ends lying in a common plane.
Type: Application
Filed: Oct 29, 2009
Publication Date: May 5, 2011
Inventors: Jun Lu (San Jose, CA), François Hébert (San Mateo, CA)
Application Number: 12/608,853
International Classification: H01L 23/52 (20060101); H01L 21/98 (20060101); H01L 23/495 (20060101);