Packaging Structures of Integrated Circuits

Abstract

A chip includes a dummy connector disposed at a top surface of the chip. A seal ring encircles a region directly underlying the dummy connector, with the region overlapping the dummy connector.

Description

BACKGROUND

In the packaging of integrated circuits, dies may be packaged onto other package components such as package substrates, interposers, printed circuit boards (PCBs), or the like. The packaging may be performed through flip chip bonding.

Since the coefficients of thermal expansion (CTE) of the dies and the CTEs of different package components may be significantly different from each other, after the flip chip bonding is performed, a significant stress may be generated in the resulting package. The stress may also be applied on the dies and other package components in the respective packages. With the increase in the sizes of the dies and the package components, the stress may be further increased, and hence a more significant problem has been observed in recent manufacturing processes, in which larger dies are used. Typically, the stress is highest at the corners of the dies because the corners have the highest distances to neutral points (DNP). The stress may cause solder cracking, dielectric cracking, and/or delamination between the dielectric layers in the dies, especially when lead-free solder is used in the package. The cracks and the delamination may propagate to other parts of the dies, causing circuit failure.

Various solutions were proposed to solve the problem caused by the high stress. In some solutions, since the corner bumps are most likely to have stresses, the structures adjacent to the corner bumps are enhanced. In some other solutions, the corner bumps are designed as dummy bumps, which are not used for electrical connection. Instead, the dummy corner bumps are used for absorbing the stresses.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1 through 3 are top views of chips in accordance with various embodiments, wherein protective seal rings are formed to encircle the regions under dummy bumps in order to prevent the propagation of the cracking and delamination in dielectric layers; and

FIGS. 4 and 5 are cross-sectional views of the chip shown in FIGS. 1 through 3.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.

A method of improving the reliability of flip chip packages and the respective circuit structures are provided in accordance with embodiments. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIG. 1 illustrates a top view of chip 20 in accordance with various embodiments, wherein chip 20 may be a device chip including active devices such as transistors therein. Chip 20 may have a rectangular top-view shape, and possibly a square top-view shape. Chip 20 includes edges 20A and corners 20B. Seal ring 22 is disposed at the peripheral regions of chip 20. For example, seal ring 22 may include four sides, with each of the sides adjacent to, and may be parallel to, one of edges 20A of chip 20. The distance S1 between the sides of seal ring 22 and the nearest edges 20A of chip 20 may be smaller than about 100 μm in some embodiments. It is realized, however, that the dimensions recited throughout the description are merely examples, and may be changed to different values. Optionally, there may be a sacrificial seal ring (not shown) formed outside, and encircling, seal ring 22.

A plurality of connectors 24 are disposed at the surface of chip 20, and may be located inside seal ring 22. Connectors 24 may be used to bond to, and electrically connect to, another package component such as a device die, an interposer, a package substrate, a printed circuit board (PCB), or the like. Connectors 24 are alternatively referred to as bumps 24, and may have various forms such as solder balls, copper pillars, solder caps, and/or the like. The bonding between chip 20 and the other package component may be made through active bumps (alternatively referred to as active electrical connectors) 24A and dummy bumps (alternatively referred to as dummy connectors) 24B. Bumps 24 may be distributed as an array, which includes a plurality of rows and columns.

Dummy bumps 24B may be disposed as corner bumps, which are adjacent to corners 20B of chip 20. Depending on the magnitude of the stress applied to the bumps, at each corner 20B, there may be one, two, three, or more dummy bumps. In some embodiments, there may be one or more dummy bumps disposed at the center of chip 20. In an exemplary embodiment, in the top view (as shown in FIG. 1) of chip 20, each of dummy bumps 24B is encircled by one protective seal ring 30, which is formed simultaneously with the formation of seal ring 22. Throughout the description, when a dummy bump is referred to as being “encircled” by a protective seal ring, it indicates that a region directly under the dummy bump (please refer to FIGS. 4 and 5) is encircled by the protective seal ring, although in the cross-sectional views such as what are shown in FIGS. 4 and 5, protective seal rings 30 are actually disposed under the respective dummy bumps 24B. Protective seal rings 30 may be electrically and/or physically disconnected from, although they may be connected to, seal ring 22. Protective seal rings 30 and seal ring 22 may be formed simultaneously in the same process steps. Accordingly, protective seal rings 30 and seal ring 22 extend into the same layers (which may be low-k dielectric layers) of chip 20. In an embodiment, none of active bumps 24A in chip 20 is encircled (viewed in the top view) by any protective seal ring(s) 30. In alternative embodiments, some of active bumps 24A in chip 20 may be encircled (viewed in the top view) by protective seal ring(s) 30.

FIG. 2 illustrates an alternative embodiment similar to the embodiment shown in FIG. 1, except two or more dummy bumps 24B are encircled by a same protective seal ring 30. In accordance with some embodiments, one protective seal ring 30 may be formed to encircle all dummy bumps 24B that are adjacent to the same corner 20B, although more than one protective seal ring 30 may be formed adjacent to the same corner 20B in alternative embodiments. In addition, in these embodiments, the protective seal ring 30 that encircles two or more dummy bumps 24B may not encircle any active bump 24A therein.

FIG. 3 illustrates yet another embodiment, wherein protective seal ring 30 and seal ring 22 may share a common portion. Protective seal ring 30 thus may include a first portion shared with seal ring 22, and an additional portion not shared with seal ring 22. The additional portion not shared with seal ring 22 may be encircled by seal ring 22. In these embodiments, protective seal ring 30 may encircle a single dummy bump 24B, or a plurality of neighboring dummy bumps 24. FIG. 3 illustrates various possible schemes for forming protective seal rings 30 at different corners of chip 20. It is realized that each of the schemes may be used at all corners of a same chip, or different schemes may be disposed in a same chip in a mixed fashion.

The embodiments shown in FIGS. 1 through 3 may be adopted on a same chip. For example, in the chip, a first protective seal ring 30 may encircle a single dummy bump 24B (FIG. 1), while a second protective seal ring 30 in the chip may encircle two or more dummy bumps 24B. A third protective seal ring 30 in the chip, on the other hand, may be formed using the scheme shown in FIG. 3.

In the embodiments shown in FIG. 1, since protective seal rings 30 encircling individual dummy bumps 24B are separated from each other, and are possibly separated from seal ring 22, the spaces between neighboring protective seal rings 30, and the spaces between protective seal rings 30 and seal ring 22 may be used for routing metal lines, which may be disposed in low-k dielectric layers. Line 25 represents an exemplary metal line routed between dummy bumps 24B (please also refer to metal lines 42 and dielectric layers 54 in FIGS. 4 and 5). On the other hand, in the embodiments in FIGS. 2 and 3, the spaces between neighboring dummy bumps 24B, and between dummy bumps 24B and seal ring 22, are also encircled by protective seal ring 30, and may not be used for routing metal lines. The design and the placement of the protective rings thus need to take these factors into consideration.

FIGS. 4 and 5 illustrate cross-sectional views of portions of chip 20, wherein the cross-sectional views are retrieved from the plane crossing line 4-4 in FIG. 2 and the plane crossing line 5-5 in FIG. 3, respectively. Chip 20 may include semiconductor substrate 40, which may be a silicon substrate, or may be formed of other semiconductor materials such as silicon carbon, silicon germanium, III-V compound semiconductor materials, or the like. Each of seal ring 22 and protective seal rings 30 includes a plurality of metal lines 42 and vias 44 formed in dielectric layers 54. In each of protective seal rings 30, at least some, and possibly each, of metal lines 42 and vias 44 may form a ring encircling region 50, which region is directly underlying and overlapping the respective dummy bump 24B. Accordingly, each of protective seal rings 30 encircles region 50 that is directly underlying the respective dummy bump 24B. From the top view, dummy bump 24B thus appears as being encircled by the respective protective seal ring 30.

Metal lines 42 and vias 44 are formed in dielectric layers 54. The dielectric constants (k values) of dielectric layers 54 may be lower than about 3.0, or lower than about 2.5, hence dielectric layer 54 may be referred to as low-k dielectric layers. The bottom metal lines 42 (in the bottom metal layer, commonly known as M1) may be formed using a single damascene process, while upper metal lines 42 may be formed along with the underlying vias 44 using dual damascene processes. The top metal layer Mtop may be formed in a low-k dielectric layer, while an overlying dielectric layer 56 immediately over the top metal layer Mtop may be formed of a non-low-k dielectric layer, and may be referred to as a passivation layer.

Seal ring 22 and protective seal rings 30 may be formed simultaneously using lithography, polish, and deposition processes, and may be formed using the same lithography masks. Accordingly, seal ring 22 and protective seal rings 30 extend into the same layers (such as metal layers M1 through Mtop) of chip 20. In some embodiments, seal ring 22 and protective seal rings 30 extend from bottom metal layer M1 into top metal layer Mtop, and does not extend into passivation layer 56. Accordingly, seal ring 22 and protective seal rings 30 may be copper-containing features. In alternative embodiments, seal ring 22 and protective seal rings 30 may also extend into passivation layers 56 that are formed of non-low-k dielectric materials. Accordingly, in accordance with some embodiments, seal ring 22 and protective seal rings 30 may include aluminum-containing features that include aluminum copper, for example.

As shown in FIGS. 4 and 5, active bumps 24A and dummy bumps 24B may have essentially the same structure and/or size, although they may also have different structures and/or sizes. In some embodiments, active bumps 24A and dummy bumps 24B are solder balls. In alternative embodiments, active bumps 24A and dummy bumps 24B may include copper pillars and solder caps formed on the copper pillars. In addition, additional layers such as a palladium layer, a gold layer, a nickel layer, or the like, may be incorporated in each of active bumps 24A and dummy bumps 24B. Active bumps 24A have electrical functions, and may be electrically coupled to metal lines, vias, active devices 60 (which may be transistors), and the like, inside chip 20. Dashed lines 58, metal lines 42, and via 44 symbolize the electrical coupling. On the other hand, dummy bump 24B does not have electrical functions, and may not be electrically coupled to any active devices such as transistors inside chip 20. An “x” sign is shown in FIG. 4 to indicate the electrical decoupling of dummy bump 24B from other devices in chip 20. The solder used in bumps 24 may be a lead-free solder, although it may be formed of other types of solders such as a eutectic solder. Furthermore, when chip 20 is bonded to another package component such as another device die, an interposer, a package substrate, a PCB, or the like, dummy bumps 24B may, or may not, be electrically coupled to other devices, metal lines, and/or vias in the other package component.

Since dummy bumps 24B are disposed where the stresses are high, delamination and cracking may still occur to the dielectric materials (which may be low-k dielectric materials) that are directly underlying dummy bumps 24B. For example, as shown in FIG. 4, cracking or delamination may occur in region 50. If the cracking or delamination occurs in region 50, the cracking or delamination will be blocked by the respective protective seal ring 30, and will not propagate to other regions in chip 20. The reliability of the resulting package is thus improved. It is observed that since protective seal rings 30 and the respective seal ring(s) 22 in the same chip are formed simultaneously, there is no additional manufacturing cost.

In accordance with embodiments, a chip includes a dummy connector disposed at a top surface of the chip. A protective seal ring encircles a region directly underlying the dummy connector, with the region overlapping the dummy connector.

In accordance with other embodiments, a chip includes a seal ring disposed in peripheral regions of the chip, wherein the peripheral regions are adjacent to edges of the chip. A plurality of dummy connectors is disposed at a top surface of the chip and adjacent to the seal ring. A plurality of active electrical connectors is disposed at the top surface of the chip. A plurality of protective seal rings is disposed in the chip, wherein each of the protective seal rings encircles a region directly underlying one of the plurality of dummy connectors. The plurality of protective seal rings is separated from each other. The plurality of protective seal rings may further be separated from the seal ring.

In accordance with yet other embodiments, a chip includes a seal ring disposed in peripheral regions of the chip, wherein the peripheral regions are adjacent to edges of the chip. A dummy connector is disposed at a top surface of the chip. The dummy connector is further adjacent to a corner of the chip. A protective seal ring encircles a region directly under the dummy connector. The protective seal ring and the seal ring share a common portion, which may be a corner portion of the seal ring.

Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.

Claims

1. A device comprising:

a first chip comprising: a dummy connector disposed at a top surface of the first chip, wherein the dummy connector is not adjacent to at least one of edges of the first chip; and a seal ring encircling a region directly underlying the dummy connector, with the region overlapping the dummy connector; and

a second chip comprising a connector disposed at a top surface of the second chip, wherein the second chip is connected to the first chip and the connector is connected to the dummy connector.

2. The device of claim 1, wherein in a top view of the first chip, the seal ring does not encircle any active electrical connector in the first chip.

3. The device of claim 1, wherein the first chip further comprises:

a plurality of dummy connectors disposed at the top surface of the first chip; and

a plurality of seal rings, wherein in a top view of the first chip, each of the seal rings encircles one of the plurality of dummy connectors, and wherein each of the plurality of seal rings is separated from each other.

4. The device of claim 1 further comprising an additional seal ring disposed in a peripheral region of the first chip and adjacent to edges of the first chip, and wherein the seal ring and the additional seal ring extend into same layers of the first chip.

5. The device of claim 4, wherein the seal ring is disposed in a region encircled by the additional seal ring.

6. The device of claim 4, wherein the seal ring and the additional seal ring are interconnected, and share a common portion.

7. The device of claim 1, wherein the seal ring extends into a plurality of metal layers comprising a bottom metal layer of the first chip and a top metal layer of the first chip, and wherein the seal ring comprises a metal line forming a ring in each of the plurality of metal layers, and vias interconnecting metal lines in the plurality of metal layers.

8. A device comprising:

a first chip comprising: a first seal ring disposed in peripheral regions of the first chip, wherein the peripheral regions are adjacent to edges of the first chip; a plurality of dummy connectors disposed at a top surface of the first chip and adjacent to the first seal ring; a plurality of active electrical connectors, wherein the plurality of active electrical connectors are formed of a same material, and at a same level, as the plurality of dummy connectors; and a plurality of second seal rings, wherein each of the plurality of second seal rings encircles a region directly underlying one of the plurality of dummy connectors, and wherein each of the plurality of second seal rings is separated from each other, and is separated from the first seal ring; and

a second chip comprising a plurality of connectors disposed at the top surface of the second chip, wherein the second chip is connected to the first chip and the plurality of connectors is connected to the plurality of dummy connectors.

9. The device of claim 8, wherein none of the plurality of active electrical connectors is encircled by the plurality of second seal rings.

10. The device of claim 8, wherein in a top view of the first chip, each of the plurality of second seal rings encircles a single dummy connector, and wherein the each of the plurality of second seal rings does not encircle any one of the plurality of active electrical connectors.

11. The device of claim 8, wherein the plurality of second seal rings is disposed adjacent to corner regions of the first chip, and is not adjacent to at least one of edges of the first chip.

12. The device of claim 8, wherein each of the plurality of second seal rings encircles a single one of the plurality of dummy connectors in a top view of the first chip.

13. The device of claim 8, wherein the plurality of dummy connectors, the plurality of active electrical connectors, and the plurality of second seal rings are encircled by the first seal ring in a top view of the first chip.

14. The device of claim 8, wherein the plurality of second seal rings and the first seal ring extend into same metal layers of the first chip.

15. A device comprising:

a first chip comprising: a first seal ring disposed in peripheral regions of the first chip, wherein the peripheral regions are adjacent to edges of the first chip; a dummy connector disposed at a top surface of the first chip and adjacent to a corner of the first chip; and a second seal ring encircling a region directly under the dummy connector, wherein the second seal ring and the first seal ring share a common portion; and

a second chip comprising a connector disposed at a top surface of the second chip, wherein the second chip is connected to the first chip and the connector is connected to the dummy connector.

16. The device of claim 15 further comprising a plurality of active electrical connectors at the top surface of the first chip, wherein the plurality of active electrical connectors is not encircled by any of second seal ring in the first chip.

17. The device of claim 15, wherein the second seal ring further comprises a portion not shared with the first seal ring, and wherein the portion not shared with the first seal ring is disposed inside the first seal ring.

18. The device of claim 15, wherein all dummy connectors in the first chip are encircled by additional seal rings in the chip, and wherein none of active electrical connectors in the first chip is encircled by any of the additional seal rings in the first chip.

19. The device of claim 15, wherein the second seal ring and the first seal ring extend into a same plurality of metal layers of the first chip, and wherein the second seal ring comprises a metal line forming a ring in each of the plurality of metal layers, and vias interconnecting metal lines in the plurality of metal layers.

20. The device of claim 15, wherein the second seal ring shares a corner part of the first seal ring with the first seal ring.