FINFET SEMICONDUCTOR DEVICES WITH STRESSED CHANNEL REGIONS
A FinFET device includes a substrate, a gate structure positioned above the substrate, and sidewall spacers positioned adjacent to the gate structure. An epi semiconductor material is positioned in source and drain regions of the FinFET device and laterally outside of the sidewall spacers. A fin extends laterally under the gate structure and the sidewall spacers in a gate length direction of the FinFET device, wherein the end surfaces of the fin abut and engage the epi semiconductor material. A stressed material is positioned in a channel cavity located below the fin, above the substrate, and laterally between the epi semiconductor material, the stressed material having a top surface that abuts and engages a bottom surface of the fin, a bottom surface that abuts and engages the substrate, and end surfaces that abut and engage the epi semiconductor material.
1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuit devices, and more specifically, to FinFET semiconductor devices having stressed channel regions.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as FinFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D FinFET device, typically comprises doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. In a planar FET device, the gate structure is formed above a substantially planar upper surface of the substrate. In some cases, one or more epitaxial growth processes are performed to form epi semiconductor material in recesses formed in the source/drain regions of the planar FET device. In some cases, the epi material may be formed in the source/drain regions without forming any recesses in the substrate for a planar FET device. The gate structures for such planar FET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure.
Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins C, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. In a FinFET device, the “channel-width” is estimated to be about two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width (for a tri-gate device). Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
For many early device technology generations, the gate structures of most transistor elements (planar or FinFET devices) were comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-32 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer and one or more metal layers that function as the gate electrode (HK/MG) have been implemented. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in an HK/MG gate electrode structure. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), titanium-aluminum-carbon (TiALC), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique.
Generally, the replacement gate process may be used when forming either planar devices or 3D devices.
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Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 20-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NMOS transistors and create a compressive stress in the channel region for PMOS transistors). Stress engineering techniques typically involve the formation of specifically made silicon nitride layers that are selectively formed above appropriate transistors, i.e., a layer of silicon nitride that is intended to impart a tensile stress in the channel region of a NMOS transistor would only be formed above the NMOS transistors. Such selective formation may be accomplished by masking the PMOS transistors and then blanket depositing the layer of silicon nitride, or by initially blanket depositing the layer of silicon nitride across the entire substrate and then performing an etching process to selectively remove the silicon nitride from above the PMOS transistors. Conversely, for PMOS transistors, a layer of silicon nitride that is intended to impart a compressive stress in the channel region of a PMOS transistor is formed above the PMOS transistors. The techniques employed in forming such nitride layers with the desired tensile or compressive stress are well known to those skilled in the art.
As noted above, as the channel length of the transistors has decreased, the pitch between adjacent transistors likewise decreases, thereby limiting the area of space between the transistors. For example, current-day transistors may be fabricated with a channel length that ranges from 20-30 nm with a gate pitch that ranges from 50-70 nm, which results in a spacing between the sidewall spacers on adjacent gate structures of about 10-20 nm. Formation of stress-inducing layers in such a small space is very difficult and it can lead to problems, such as the formation of voids, which may limit the effectiveness of such stress-inducing layers.
The present disclosure is directed to various methods of forming a stressed channel region for a FinFET semiconductor device and the resulting semiconductor device that may avoid, or at least reduce, the effects of one or more of the problems identified above.
SUMMARY OF THE DISCLOSUREThe following presents a simplified summary of the disclosure in order to provide a basic understanding of some aspects of the subject matter that is described in further detail below. This summary is not an exhaustive overview of the disclosure, nor is it intended to identify key or critical elements of the subject matter disclosed here. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various methods of forming a stressed channel region for a FinFET semiconductor device and the resulting semiconductor device. In one illustrative embodiment, a FinFET device is disclosed that includes, among other things, a substrate of a first semiconductor material, a gate structure positioned above the substrate, and sidewall spacers positioned adjacent to the gate structure. Additionally, the illustrative FinFET device includes an epi semiconductor material that is positioned in source and drain regions of the FinFET device and laterally outside of the sidewall spacers, wherein the epi semiconductor material includes a second semiconductor material, and a fin that extends laterally under the gate structure and the sidewall spacers in a gate length direction of the FinFET device, wherein the end surfaces of the fin abut and engage the epi semiconductor material. Furthermore, the FinFET device also includes a stressed material positioned in a channel cavity that is located below the fin, above the substrate, and laterally between the epi semiconductor material, wherein the stressed material has a top surface that abuts and engages a bottom surface of the fin, a bottom surface that abuts and engages the substrate, and end surfaces that abut and engage the epi semiconductor material.
Also disclosed herein is an exemplary FinFET device that includes a lower fin structure that is defined in a substrate, the lower fin structure including a first semiconductor material, and an upper fin structure that is positioned above the lower fin structure, wherein the upper fin structure has opposing end surfaces and a bottom surface that is separated from a top surface of the lower fin structure by a channel cavity that extends in a gate length direction of the FinFET device between source and drain regions thereof, the upper fin structure including a second semiconductor material. Furthermore, the illustrative FinFET device also includes, among other things, a gate structure positioned above and around the upper fin structure, and an epi semiconductor material positioned in each of the source and drain regions of the FinFET device and include a third semiconductor material, wherein the opposing end surfaces of the upper fin structure abut and engage the epi semiconductor material. Additionally, the disclosed FinFET device further includes a stressed material positioned in the channel cavity, the stressed material having a top surface that abuts and engages the bottom surface of the upper fin structure, a bottom surface that abuts and engages the top surface of the lower fin structure, and opposing end surfaces that abut and engage the epi semiconductor material.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.
DETAILED DESCRIPTIONVarious illustrative embodiments of the present subject matter are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various systems, structures and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
Generally, present disclosure relates to various methods of forming a stressed channel region for a FinFET semiconductor device and the resulting semiconductor device. Moreover, as will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc., and the methods disclosed herein may be employed to form N-type or P-type semiconductor devices. The methods and devices disclosed herein may be employed in manufacturing products using a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., and they may be employed in manufacturing a variety of different devices, e.g., memory devices, logic devices, ASICs, etc. As will be appreciated by those skilled in the art after a complete reading of the present application, the inventions disclosed herein may be employed in forming integrated circuit products using a variety of so-called 3D devices, such as FinFETs. For purposes of disclosure, reference will be made to an illustrative process flow wherein a single FinFET device 100 is formed. Moreover, the inventions will be disclosed in the context of forming the gate structures using a replacement gate (“gate-last”) processing technique. Of course, the inventions disclosed herein should not be considered to be limited to the illustrative examples depicted and described herein. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
In one embodiment, the illustrative device 100 will be formed in and above the semiconductor substrate 102, having a bulk configuration. The device 100 may be either an NMOS or a PMOS transistor. Additionally, various doped regions, e.g., source/drain regions, halo implant regions, well regions and the like, are not depicted in the attached drawings. The substrate 102 may be made of silicon or it may be made of materials other than silicon. In other embodiments, the device 100 may be formed on a so-called silicon-on-insulator (SOI) substrate, as described more fully below. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials.
The attached drawings present various views of one illustrative embodiment of a FinFET device 100 that may be formed using the methods disclosed herein.
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As will be appreciated by those skilled in the art, the presently disclosed inventions also provide device designers with greater flexibility in manufacturing CMOS-based integrated circuit devices. For example, in some applications, the structure depicted in
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1. A FinFET device, comprising:
- a substrate comprising a first semiconductor material;
- a gate structure positioned above said substrate;
- sidewall spacers positioned adjacent to said gate structure;
- an epi semiconductor material positioned in source and drain regions of said FinFET device and laterally outside of said sidewall spacers, said epi semiconductor material comprising a second semiconductor material;
- a fin extending laterally under said gate structure and said sidewall spacers in a gate length direction of said FinFET device, wherein end surfaces of said fin abut and engage said epi semiconductor material; and
- a stressed material positioned in a channel cavity that is located below said fin, above said substrate, and laterally between said epi semiconductor material, said stressed material having a top surface that abuts and engages a bottom surface of said fin, a bottom surface that abuts and engages said substrate, and end surfaces that abut and engage said epi semiconductor material.
2. The FinFET device of claim 1, wherein said stressed material comprises a stressed semiconductor material.
3. The FinFET device of claim 1, wherein said stressed material comprises one of a nitride material, an oxide material, and a metal-containing material.
4. The FinFET device of claim 1, wherein said stressed material is one of a tensile-stressed material and a compressive-stressed material.
5. The FinFET device of claim 1, wherein said substrate is silicon and said epi semiconductor material is silicon/germanium.
6. The FinFET device of claim 1, wherein said fin comprises said first semiconductor material.
7. The FinFET device of claim 1, wherein said first semiconductor material is different from said second semiconductor material.
8. The FinFET device of claim 1, wherein said gate structure comprises a gate insulation layer comprising a high-k insulating material and a gate electrode comprising at least one layer of metal.
9. A FinFET device, comprising:
- a lower fin structure defined in a substrate, said lower fin structure comprising a first semiconductor material;
- an upper fin structure positioned above said lower fin structure, wherein said upper fin structure has opposing end surfaces and a bottom surface that is separated from a top surface of said lower fin structure by a channel cavity that extends in a gate length direction of said FinFET device between source and drain regions thereof, said upper fin structure comprising a second semiconductor material;
- a gate structure positioned above and around said upper fin structure;
- an epi semiconductor material positioned in each of said source and drain regions of said FinFET device and comprising a third semiconductor material, wherein said opposing end surfaces of said upper fin structure abut and engage said epi semiconductor material; and
- a stressed material positioned in said channel cavity, said stressed material having a top surface that abuts and engages said bottom surface of said upper fin structure, a bottom surface that abuts and engages said top surface of said lower fin structure, and opposing end surfaces that abut and engage said epi semiconductor material.
10. The FinFET device of claim 9, further comprising sidewall spacers positioned adjacent to said gate structure, wherein said upper fin structure and said stressed material extend laterally under said sidewall spacers, and wherein said epi semiconductor material is positioned laterally adjacent to and outside of said sidewall spacers.
11. The FinFET device of claim 9, wherein said stressed material comprises a stressed semiconductor material.
12. The FinFET device of claim 9, wherein said stressed material comprises one of a nitride material, an oxide material, and a metal-containing material.
13. The FinFET device of claim 9, wherein said stressed material is one of a tensile-stressed material and a compressive-stressed material.
14. The FinFET device of claim 9, wherein said first semiconductor material is silicon and said third semiconductor material is silicon/germanium.
15. The FinFET device of claim 9, wherein said first and second semiconductor materials are a same semiconductor material.
16. The FinFET device of claim 9, wherein said first semiconductor material is different from said third semiconductor material.
17. The FinFET device of claim 9, wherein said gate structure comprises a gate insulation layer comprising a high-k insulating material and a gate electrode comprising at least one layer of metal.
Type: Application
Filed: Jun 20, 2016
Publication Date: Oct 6, 2016
Inventors: Xiuyu Cai (Niskayuna, NY), Ruilong Xie (Niskayuna, NY), Kangguo Cheng (Schenecdtady, NY), Ali Khakifirooz (Mountain View, CA), Ajey P. Jacob (Watervliet, NY), Witold P. Maszara (Morgan Hill, CA)
Application Number: 15/186,632