Abstract: A semiconductor device includes a nanostructure field effect transistor (FET). The FET includes a gate and a source or drain (S/D) region. The FET also includes a backside S/D contact connected to a top surface of the S/D region. The backside S/D contact includes a lateral portion upon the top surface of the S/D region. The lateral portion further laterally extends adjacent to or past the first S/D region. The backside S/D contact includes a vertical portion that extends vertically downward from the lateral portion below the bottom surface of the substrate layer. The FET also includes a backside S/D mushroom that extends vertically downward from the vertical portion.

Abstract: A semiconductor structure is provided that includes a backside bitline connected to a dynamic random access memory (DRAM) cell that includes a plurality of field effect transistors (FETs) and a plurality of DRAM capacitors that are present in a frontside of the structure.

Abstract: A semiconductor device includes a first source/drain element on a first side of the semiconductor device, a second source/drain element on an opposing side of the semiconductor device, a backside contact including a first contact end on a first end of the first source/drain element and an opposing contact end in electrical communication with a backside power distribution network, a critical dimension of the first contact end is smaller than the critical dimension of the opposing contact end, and the backside contact is substantially aligned to the first source/drain element. The semiconductor device also includes and a source/drain placeholder material with a critical dimension of a middle portion of the source/drain placeholder material being larger than the critical dimension of both tend portions.

Abstract: Embodiments of present invention provide an interconnect structure. The interconnect structure includes a first metal line in a first inter-level dielectric (ILD) layer; one or more second metal lines in a second ILD layer above the first metal line and above the first ILD layer; a third metal line in a third ILD layer above the one or more second metal lines and above the second ILD layer; and a skipvia connecting the third metal line with the first metal line, wherein the first, the one or more second, and the third metal lines are made of a first conductive material and the skipvia is made of a second conductive material, and the first conductive material is different from the second conductive material. A method of forming the above interconnect structure is also provided.

Abstract: A stacked field effect transistor (stacked-FET) device includes a first layer comprising at least one first layer transistor structure comprising a plurality of first layer terminals, a diffusion break dielectric fill region adjacent to one of the first layer terminals, a second layer overlying and adjacent to the first layer and comprising at least one second layer transistor structure comprising a plurality of second layer terminals, and a contact wiring between the first layer and the second layer passing through the diffusion break dielectric fill region of the first layer and connecting with one of the second layer terminals.

Abstract: A semiconductor structure is provided that includes a device layer and a non-perpendicular (or non-orthogonal) wiring layer that includes a skip-level via that connects this wiring level to the device layer. The skip-level via passes through another wiring layer that is positioned between the non-perpendicular wiring layer and the device layer, without physically contacting any metal lines that are present in this another wiring layer.

Abstract: A semiconductor structure includes a source/drain region having a backside surface disposed in a backside interlayer dielectric layer, a backside contact disposed in the backside interlayer dielectric layer, wherein the backside contact is disposed on the backside surface of the source/drain region, backside sidewall spacers disposed between sidewalls of the backside interlayer dielectric layer and sidewalls of the backside contact and the backside surface of the source drain region, and a backside power rail connected to the source/drain region through the backside contact.

Abstract: An interconnect structure includes a first metallization layer, a second metallization layer, and a via metallization layer connecting the first metallization layer to the second metallization layer. The via metallization layer includes a metal via having a first portion extending in a first direction and a second portion extending from the first portion in a second direction different than the first direction.

Abstract: A semiconductor memory cell comprising six vertical-transport field-effect transistors (VTFET) on a wafer. The six VTFET are in a first layer. The six VTFET are in a first row.

Abstract: Monolithically stacked VTFET devices having source/drain contacts with increased contact area and dielectric isolation are provided. In one aspect, a stacked VTFET device includes: at least a bottom VTFET below a top VTFET, wherein the bottom VTFET and the top VTFET each includes source/drain regions interconnected by a vertical fin channel, and a gate stack alongside the vertical fin channel; and source/drain contacts to the source/drain regions, wherein at least one of the source/drain contacts is in direct contact with more than one surface of a given one of the source/drain regions. A stacked VTFET device having at least a bottom VTFET1 below a top VTFET1, and a bottom VTFET2 below a top VTFET2, and a method of forming a stacked VTFET device are also provided.

Abstract: A deep-via structure includes at least one via-interfacing layer. The deep-via structure also includes a via. The via is embedded within the at least one via-interfacing layer. The via includes a conductive material. The deep-via structure also includes a stress-relief void that is formed within the conductive material of the via.

Abstract: A semiconductor structure comprises a source/drain region, a spacer layer on a first side of the source/drain region, a contact on a top surface of the source/drain region, and a via connected to a portion of the contact at a second side of the source/drain region, the second side of the source/drain region being opposite the first side of the source/drain region.

Abstract: Embodiments of the invention include an isolation layer under a nanosheet stack of a transistor and a graded layer under the isolation layer. The graded layer includes an impurity gradient.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor chip having a frontside and a backside; a first metal level at the backside of the semiconductor chip; a second metal level above the first metal level; a plurality of damascene vias extending from the second metal level towards the first metal level; and a plurality of subtractive vias extending from the first metal level towards the second metal level, wherein the plurality of damascene vias and the plurality of subtractive vias are staggered to form an interdigitated comb-comb structure. A method of forming the semiconductor structure is also provided.

Abstract: A vertical transport field effect transistor (VTFET) apparatus includes a fin-shaped channel structure; a gate stack that surrounds the channel structure; a top source/drain structure at a top end of the channel structure; a top interconnect layer above the top source/drain structure; a top contact that electrically connects the top source/drain structure to the top interconnect layer; a bottom source/drain structure at a bottom end of the channel structure; a backside interconnect layer below the bottom source/drain structure; and a backside contact that touches a bottom surface of the bottom source/drain structure and also touches a side surface of the bottom source/drain structure and electrically connects the bottom source/drain structure to the backside interconnect layer.

Abstract: A semiconductor structure including a stacked transistor structure comprising a top device stacked directly above a bottom device, and a bilayer gate dielectric layer separating the top device from the bottom device.

Abstract: A semiconductor structure includes a first transistor device, a second transistor device, and a dielectric pillar structure disposed between the first transistor device and the second transistor device. The dielectric pillar structure includes a first dielectric pillar adjacent the first transistor device and a second dielectric pillar adjacent the second transistor device.

Abstract: A semiconductor device includes a field effect transistor (FET) with at least one Gate-All-Around (GAA) channel. A first conductive ferromagnetic Source/Drain contact is electrically connected with a first portion of the GAA channel. A second conductive ferromagnetic Source/Drain contact is electrically connected with a second portion of the GAA channel. A remanent magnetization of the first conductive ferromagnetic contact is oriented in a direction opposite to a remanent magnetization of the second conductive ferromagnetic contact.

Abstract: A device structure for a phase-change memory device is disclosed. The device structure includes a top electrode, a phase-change material that is recessed between two layers of resistive liner material, and a conductive material. The conductive material contacts the sidewall of the top electrode, the sidewall of the phase-change material, and a portion of a top surface and a bottom surface of each of the two layers of the resistive liner material. The device structure includes a heater contacting a bottom electrode and the bottom layer of the resistive liner material. The heater is in a first bilayer dielectric. A second bilayer dielectric is under the top electrode.

Abstract: Embodiments of the invention include a transistor comprising a gate region and a source/drain region. A first isolation layer is under the gate region. A second isolation layer is separated from the first isolation layer by a third isolation layer.