SELF-ALIGNED GATE TIE-DOWN CONTACTS WITH SELECTIVE ETCH STOP LINER
A method for forming a gate tie-down includes exposing an active area to form trench contact openings and forming trench contacts therein. An etch stop layer is formed on the trench contacts and on spacers of adjacent gate structures. An interlevel dielectric (ILD) is deposited to fill over the etch stop layer. The ILD and the etch stop layer on one side of the gate structure are opened up to provide an exposed etch stop layer portion. The gate structure is recessed to expose a gate conductor. The exposed etch stop layer portion is removed. A conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.
Technical Field
The present invention relates to semiconductor processing, and more particularly to a gate tie-down structure that permits gate contacts in active areas and reduces shorts between adjacent contacts and gate conductors.
Description of the Related Art
In conventional complementary metal oxide semiconductor (CMOS) processing, gate contacts are formed over shallow trench isolation (STI) regions. Gate contacts connect a gate line to upper metal layers in device designs. In many instances, providing the gate contacts in STI regions can result in a large amount of chip area being lost.
Gate tie-down structures or regions provide a connection between the gate contact and a source/drain (S/D) region contact. The formation of a gate tie-down structure may result in shorts between a silicide region of the S/D region or with conductive material of an adjacent gate. This is due, in part, to the small margins of dielectric materials between these structures and the close proximity of the conductive bodies.
SUMMARYA method for forming a gate tie-down includes exposing an active area by etching dielectric material on adjacent sides of a gate structure to open up trench contact openings; forming trench contacts in the trench contact openings and forming an etch stop layer on the trench contacts and on spacers of gate structures adjacent to the trench contacts. An interlevel dielectric (ILD) is deposited to fill over the etch stop layer in the trench contact openings and over the gate structures adjacent to the trench contacts. The ILD and the etch stop layer on one side of the gate structure are opened up to provide an exposed etch stop layer portion. The gate structure is recessed to remove a cap layer, recess one spacer and expose a gate conductor. The exposed etch stop layer portion is removed. A conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.
Another method for forming a gate tie-down includes exposing an active area by etching dielectric material on adjacent sides of a gate structure to open up trench contact openings; depositing a first conductive material in the trench contact openings; recessing the first conductive material to form trench contacts in the trench contact openings; conformally depositing an etch stop layer on the dielectric material, on the trench contacts and on spacers of gate structures adjacent to the trench contacts; forming a planarizing material over the etch stop layer; planarizing to remove the planarizing material and the etch stop layer from a top surface; removing the planarizing material from etch stop portions formed on the trench contacts; depositing an interlevel dielectric (ILD) to fill over the etch stop portions and over the gate structures adjacent to the trench contacts; opening up the ILD and the etch stop portion on one side of the gate structure to provide an exposed etch stop layer portion; recessing the gate structure to remove a cap layer, recess one spacer and expose a gate conductor; removing the exposed etch stop layer portion; and depositing a second conductive material to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.
A gate tie-down structure includes a gate structure including a gate conductor and gate spacers, trench contacts formed on sides of the gate structure and an etch stop layer portion formed on a gate spacer on one side of the gate structure and over the trench contact on the one side of the gate structure. A first interlevel dielectric (ILD) is configured to bury the gate structure, and a second interlevel dielectric (ILD) has a thickness and is formed on the first ILD and over the etch stop layer portion. A self-aligned contact connects to the trench contact on the other side of the gate structure. A gate contact is connected to the gate conductor. A horizontal connection within the thickness of the second ILD is formed over an active area and connects the gate conductor and the self-aligned contact over a gate spacer formed on the other side of the gate structure.
These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:
In accordance with the present principles, a gate tie-down structure and methods for fabrication are provided. The gate tie-down provides a gate contact (CB) that is able to short against a self-aligned contact (CA) without shorting against a trench silicide (TS) contact. The gate contact provides a connection to a gate conductor (PC) of a gate structure employed in a transistor device. The gate conductor in some instances may be connected to a source or drain region. This is referred to as a gate tie-down. Gate tie-downs in accordance with the present principles may be provided over active regions without suffering from the shorting issues of conventional structures.
The present principles provide methods and structures for forming gate-tie-downs with an etch stop layer, e.g., high-k dielectric, to encapsulate source/drain contacts. This etch stop layer prevents breakthrough into adjacent gate conductors. In addition, the gate tie-downs include a gate contact that is self-aligned to a source/drain contact. The tie-down structure provides a gate contact that can “fly” over the source/drain contact making the design more compact saving precious chip area. For example, the gate tie-down structure can be allowed on or over active areas (AA). The gate contact structure enables the gate contact to fly over a source/drain contact to reduce a layout footprint. The gate tie-down structure may be employed in memory devices, e.g., static random access memory (SRAM), processors, or other chip devices.
It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present invention.
It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
The present embodiments may be included in an integrated circuit or integrated circuit design. A design for an integrated circuit chip may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
Methods as described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
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In accordance with the present principles, the gate tie-down structure 66 provides a self-aligned gate contact (CB) 64 that shorts directly to contact 62 (CA) and not directly to the TS contact 36. A spacer 68 along with the etch stop layer 38 prevents shorts between the adjacent contact 36 and the gate conductor 22. A spacer 70 prevents shorts between the adjacent contact 36 and the gate conductor 22 (shorts in this region occurred in conventional structures). A spacer 72 provides a dielectric barrier that prevents direct shorting between the gate contact 64 and the TS contact 36. In addition, the gate contact 64 is self-aligned with the self-aligned contact 36. The gate contact 64 is made within the active region (over S/D regions 26). This reduces the layout footprint of the device 10. In other words, a horizontal connection 74 is made directly between the gate contact 64 and the self-aligned contact 62 using vertical space provided by the ILD 42. This connection 74 is made without having to use layout area, which would normally be consumed by placing the connections over an STI region outside of the S/D regions (active area). The present principles may be implemented in 7 nm technology, although other technology sizes (larger or smaller may benefit from the present principles).
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In block 102, after gate structures and source and drain (S/D) regions are formed, an active area is exposed by etching dielectric material on adjacent sides of a gate structure to open up trench contact openings. In block 104, a conductive material is deposited in the trench contact openings. In block 106, the conductive material is recessed to form trench contacts in the trench contact openings. In block 108, an etch stop layer is conformally deposited on the dielectric material, on the trench contacts and on spacers of gate structures adjacent to the trench contacts. The etch stop layer may include a high-k dielectric material.
In block 110, a planarizing material is optionally formed over the etch stop layer. The planarizing material may include a spun on organic material. In block 112, planarizing material and the etch stop layer are planarized to remove them from a top surface. In block 114, the planarizing material is removed from etch stop portions formed on the trench contacts.
In block 116, an interlevel dielectric (ILD) is deposited to fill over the etch stop portions and over the gate structures adjacent to the trench contacts. In block 118, the ILD and the etch stop portion are opened up on one side of the gate structure to provide an exposed etch stop layer portion. In block 120, the gate structure is recessed to remove a cap layer, recess one spacer and expose a gate conductor. The recessed spacer remains to permit contact between a self-aligned contact and a gate contact (which will be formed) and to prevent contact between the trench contact and the gate conductor.
In block 122, the exposed etch stop layer portion is removed. In block 124, another conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact. The etch stop portion opposite the one side of the gate structure remains with a corresponding spacer of the gate structure to prevent shorts between one of the trench contacts and the gate conductor. The exposed etch stop layer portion prevents erosion of a spacer of an adjacent gate structure to prevent shorts between one of the trench contacts and a gate conductor of an adjacent gate structure. The ILD includes a thickness above the cap layer of the gate structures, and the horizontal connection between the gate conductor and the self-aligned contact is formed within the ILD thickness. In block 126, processing continues to complete the device.
Having described preferred embodiments for gate tie-down with a highly selective etch stop liner (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
Claims
1. A gate tie-down structure, comprising:
- a gate structure including a gate conductor and gate spacers;
- trench contacts formed on sides of the gate structure;
- an etch stop layer portion formed on a gate spacer on one side of the gate structure and over the trench contact on the one side of the gate structure;
- a first interlevel dielectric (ILD) configured to bury the gate structure;
- a second interlevel dielectric (ILD) having a thickness and being formed on the first ILD and over the etch stop layer portion;
- a self-aligned contact connecting to the trench contact on the other side of the gate structure;
- a gate contact connected to the gate conductor; and
- a horizontal connection within the thickness of the second ILD formed over an active area and connecting the gate conductor and the self-aligned contact over a gate spacer formed on the other side of the gate structure.
2. The structure as recited in claim 1, wherein the etch stop layer portion prevents shorts between one of the trench contacts and the gate conductor.
3. The structure as recited in claim 1, wherein a spacer of an adjacent gate structure remains intact throughout processing due to a removed etch stop layer portion to prevent shorts between one of the trench contacts and a gate conductor of an adjacent gate structure.
4. The structure as recited in claim 1, wherein the second ILD includes a thickness above a cap layer of adjacent gate structures, and the horizontal connection between the gate conductor and the self-aligned contact is formed within the second ILD thickness.
5. The structure as recited in claim 1, wherein the gate spacer formed on the other side remains to permit contact between the self-aligned contact and the gate contact and to prevent contact between the trench contact and the gate conductor.
6. The structure as recited in claim 1, wherein the etch stop layer portion includes a high-k dielectric material.
7. The structure as recited in claim 1, wherein the structure is formed in the active area to reduce device area.
Type: Application
Filed: Dec 13, 2016
Publication Date: Mar 30, 2017
Inventors: Su Chen Fan (Cohoes, NY), Lars W. Liebmann (Poughquag, NY), Ruilong Xie (Niskayuna, NY)
Application Number: 15/377,473