Method of forming a FINFET structure
A semiconductor device (10) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting (32) of a source (14) electrode and a drain (16) electrode adjacent to an intervening gate (18) and channel (23) connected via source/drain extensions (22, 24) which form a fin. At small dimensions, ion implanting may cause irreparable crystal damage to any thin areas of silicon such as the fin area. To permit a high concentration/low resistance source/drain extension, a sacrificial doping layer (28, 30) is formed on the sides of the fin area. Dopants from the sacrificial doping layer are diffused into the source electrode and the drain electrode using heat. Subsequently a substantial portion, or all, of the sacrificial doping layer is removed from the fin.
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This invention relates generally to semiconductors, and more specifically, to making semiconductor devices having very small dimensions.
BACKGROUND OF THE INVENTIONAs transistor sizes continue to be scaled to smaller and smaller dimensions, different types of ultra thin-body transistor structures have been proposed. For example, double gated transistors permit twice the drive current and have an inherent coupling between the gates and channel that makes the design amenable to scaling.
With reduced size gate lengths, many transistors have difficulty in maintaining high drive current with low leakage while not demonstrating short-channel effects such as leakage and threshold voltage stability. Bulk silicon planar CMOS transistors typically overcome these problems by scaling polysilicon gates and oxides, using super-steep retrograde wells (often triple wells), abrupt source/drain junctions and highly doped channels. At some point, however, intense channel doping begins to degrade carrier mobility and junction characteristics.
As the length of transistor gates become ever smaller, electrostatic control of the resulting short transistor channel by the gate electrode becomes difficult. In particular, control of off-state leakage current between the source and the drain is reduced. As channel lengths are reduced, others have increased channel implants of conventional planar single-gated bulk or partially-depleted SOI (silicon on insulator) devices to improve control of electrons in the short transistor channel and reduce off-state current leakage. Unfortunately, significantly increasing the doping of the transistor's channel causes severe degradation of the channel electron mobility and thus leads to reduced transistor drive current. Other transistor structures have been proposed that improve the electrostatic control over the source/drain current leakage through a thin body structure and enhance electrostatic influence of the gate on carriers (holes or electrons) in the transistor channel. Such transistor structures include undoped ultra-thin channel devices like single-gate and multiple-gate fully-depleted devices with undoped ultra-thin channels. Multiple gate fully-depleted transistors provide the best short-channel control. The two gates control roughly twice as much current as a single gate, which allows them to produce significantly stronger switching signals. The two-gate design provides inherent electrostatic and hot-carrier coupling in the channel. This intimate coupling between the gates and channel makes double-gated MOSFET technology one of the most scalable of all FET designs.
The FINFET transistor is a double-gated MOSFET (MOS field effect transistor) device wherein the gate structure wraps around a thin silicon body that forms a structure resembling a fin. The FINFET includes a forward protruding source and a backward protruding drain, both of which extend from the gate by an extension region which is the fin. Forming the extension region or the fin is a major issue because ion implantation of the source and drain regions may cause significant damage to the extension region since is it thin and subject to full penetration by implanted ions. In particular, the ion implantation may fully amporphize the extension region resulting in a polycrystalline extension region rather than single crystalline which degrades the carrier mobility and lowers the drive current.
The present invention is illustrated by way of example and not limited to the accompanying figures, in which like references indicate similar elements.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
DETAILED DESCRIPTIONAs transistor gate lengths are reduced in size, there is a need for increasingly thinner silicon for the channel of a transistor. However this need is contrary to a need for thicker silicon in the source/drain extensions and source/drain regions in order to reduce parasitic resistance. Doped selective epitaxy may be used to thicken the source/drain extension regions. The doped selective epitaxy increases the parasitic capacitance between the transistor gate and extension region due to fringing electric fields from the side walls of the transistor's gate.
The extremely thin silicon and tall vertical structure of the fin poses several challenges to doping of source/drain extensions and source/drain regions by conventional high dose ion implantation. Very thin silicon (i.e. less than 100 Angstroms) does not have sufficient stopping power or volume to retard the high-energy dopant ions from ion implantation, leading to severe dose loss. High dose ion-implantation causes excessive crystal damage, such as amorphization, from which a thin silicon layer cannot fully recover due to insufficient silicon volume for epitaxial recrystallization. Furthermore, it is difficult to control the lateral diffusion of the source/drain dopants into the channel without the use of amorphizing implants. Also, the need to use angled and tilted implants for the source/drain extension and source/drain regions leads to vertical variation in the implant profile due to channeling in this silicon leading to sever channel length variation along the side of the tall structure.
The problems associated with doping of the source/drain extensions and source/drain regions can be overcome by providing a thick amorphous, polycrystalline, or crystalline sacrificial doping layer to be described below in connection with the figures. The sacrificial doping layer is selectively or unselectively grown on the vertical device which functions as a dopant source to dope the thin source/drain regions, source/drain extensions, or the gate through solid-phase diffusion of the dopants from the pre-doped sacrificial doping layer. The sacrificial doping layer can be pre-doped through high-level in-situ incorporation of the dopants, generally greater than E18 cm3, but can be lower, during the growth process or through high-dose ion implantation. The sacrificial dopant layer can be removed substantially or completely after the doping process depending on the need of the device structure.
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By now it should be appreciated that there has been provided a method for forming a semiconductor structure having a fin that is not damaged from proper doping of the source/drain regions and source/drain extensions. In one form there is provided a method for forming a semiconductor structure by providing a substrate and providing a semiconductor structure over the substrate. The semiconductor structure has a semiconductor fin, a first source/drain contact region adjacent to a first end of the semiconductor fin, a second source/drain contact region adjacent to a second end of the semiconductor fin, and a gate feature along a middle portion of a first side of the semiconductor fin. A first sacrificial doping layer is formed on the first side of the semiconductor fin between the first source/drain contact region and the gate feature and a second sacrificial doping layer on the first side of the semiconductor fin between the second source/drain contact and the gate feature. The first and second sacrificial doping layers are heated. After the heating, at least a substantial portion of the first sacrificial doping layer and at least a substantial portion of the second sacrificial doping layer are removed. In one form the first and second sacrificial doping layers are implanted with source/drain dopants prior to the heating. In another form the first and second sacrificial doping layers are deposited in situ doped with source/drain dopants. In one form the gate feature is replaced with a gate. In yet another form the gate feature is a gate separated from the semiconductor fin by a gate dielectric. In yet another form a sidewall spacer is formed adjacent to the gate feature prior to forming the first and second sacrificial doping layers. In yet another form the semiconductor fin is of a material that is selectively etchable with respect to the first and second sacrificial doping layers. In yet another form the semiconductor fin is silicon, the first and second sacrificial doping layers is silicon germanium, and removing the first sacrificial doping layer and the second sacrificial doping layer is performed by applying an etchant that is selective between silicon and silicon germanium. In another form the etchant is NH4 and H2O2. In yet another form the first and second sacrificial doping layers are formed by epitaxially growing silicon germanium. In another form the first and second sacrificial doping layers are implanted with source/drain dopants at an angle that deviates from vertical by at least ten degrees, wherein vertical is with respect to a top surface of the substrate. In yet another form the gate feature is provided along a middle portion of a second side of the semiconductor fin. In one form the first sacrificial doping layer is formed on the second side of the semiconductor fin between the gate feature and the first source/drain contact region and the second sacrificial doping layer is formed on the second side of the semiconductor fin between the gate feature and the second source/drain contact region. In another form the first and second sacrificial doping layers are a selected one of the group consisting of amorphous and polycrystalline.
In yet another form there is herein provided a method for forming a FinFET structure. A substrate is provided and a semiconductor fin is provided having a height and a width, wherein the height is at least five times greater than the width. A gate feature is provided along a middle portion of the semiconductor fin, the gate feature having a first side and a second side. A first sacrificial doping layer is formed on the semiconductor fin adjacent to and spaced from the first side of the semiconductor fin, and a second sacrificial layer is formed on the semiconductor fin adjacent to and spaced from the second side of the gate feature, wherein the first and second sacrificial doping layers are doped with a source/drain dopant material. The first and second sacrificial doping layers are heated to cause some of the source/drain dopants to diffuse into the first and second source/drain contact regions. An etchant is applied to the first and second sacrificial doping layers. In one form a sidewall spacer is formed adjacent to the gate feature prior to forming the first and second sacrificial doping layers. In another form the etchant is selective between the semiconductor fin and the first and second sacrificial doping layers. In yet another form the first and second sacrificial doping regions are formed by implanting the first and second sacrificial doping layers with the source/drain dopant material. In yet another form the first and second sacrificial layers are formed by depositing the first and second sacrificial layers in situ doped with the source/drain dopant material.
In yet another form there is herein provided a method of forming a semiconductor device structure. A semiconductor feature is provided having a height, width, and length protruding from a substrate. The semiconductor feature is characterized as having a first side of the height and length on a first side of the width and a second side of the height and length on a second side of the width. A gate feature is formed in a middle portion of the semiconductor feature on the first side, the second side, and the width, whereby a first source/drain extension region and a second source/drain extension region are uncovered by the gate feature. A sidewall spacer is formed on the gate feature. A dopant-transferring material is formed on the first and second source/drain extension regions. The dopant-transferring material is heated and then substantially removed. In another form the dopant-transferring material is a semiconductor material. In yet another form the dopant-transferring material is doped by a selected one of the group consisting of implanting and in-situ doping. In one form the sidewall spacer is a dielectric material and the dopant-transferring material is a different type of material than that of the semiconductor feature.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, while a single conductive gate has been illustrated, two or more electrically isolated gates may be implemented. In such an alternate form, gate feature 18 is formed as two physically separate conductive regions separated by a dielectric material.
Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms a or an, as used herein, are defined as one or more than one. The term plurality, as used herein, is defined as two or more than two. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically.
Claims
1. A method for forming a semiconductor structure, comprising:
- providing a substrate;
- providing a semiconductor structure over the substrate comprising a semiconductor fin, a first source/drain contact region adjacent to a first end of the semiconductor fin, a second source/drain contact region adjacent to a second end of the semiconductor fin, and a gate feature along a middle portion of a first side of the semiconductor fin;
- forming a first sacrificial doping layer on the first side of the semiconductor fin between the first source/drain contact region and the gate feature and a second sacrificial doping layer on the first side of the semiconductor fin between the second source/drain contact region and the gate feature;
- heating the first and second sacrificial doping layers;
- after the step of heating, removing at least a substantial portion of the first sacrificial doping layer and at least a substantial portion of the second sacrificial doping layer.
2. The method of claim 1 further comprising:
- implanting the first and second sacrificial doping layers with source/drain dopants prior to the step of heating.
3. The method of claim 1 wherein the step of forming the first and second sacrificial doping layers is further characterized as depositing the first and second sacrificial doping layers in situ doped with source/drain dopants.
4. The method of claim 1 further comprising replacing the gate feature with a gate.
5. The method of claim 1, wherein the gate feature is a gate separated from the semiconductor fin by a gate dielectric.
6. The method of claim 1 further comprising forming a sidewall spacer adjacent to the gate feature prior to the step of forming the first and second sacrificial doping layers.
7. The method of claim 1 wherein the semiconductor fin is of a material that is selectively etchable with respect to the first and second sacrificial doping layers.
8. The method of claim 1 wherein the semiconductor fin comprises silicon, the first and second sacrificial doping layers comprises silicon germanium, and removing at least the substantial portion of the first sacrificial doping layer and the second sacrificial doping layer comprises applying an etchant that is selective between silicon and silicon germanium.
9. The method of claim 8, wherein the etchant comprises NH4 and H2O2.
10. The method of claim 1 wherein the step of forming the first and second sacrificial doping layers comprises epitaxially growing silicon germanium.
11. The method of claim 1 further comprising implanting the first and second sacrificial doping layers with source/drain dopants at an angle that deviates from vertical by at least ten degrees, wherein vertical is with respect to a top surface of the substrate.
12. The method of claim 1, wherein:
- the step of providing the semiconductor structure is further characterized as providing the gate feature along a middle portion of a second side of the semiconductor fin; and
- the step of forming the first and second sacrificial doping layers is further characterized as forming the first sacrificial doping layer on the second side of the semiconductor fin between the gate feature and the first source/drain contact region and as forming the second sacrificial doping layer on the second side of the semiconductor fin between the gate feature and the second source/drain contact region.
13. The method of claim 1, wherein the first and second sacrificial doping layers are further characterized as being a selected one of the group consisting of amorphous and polycrystalline.
14. A method for forming a FinFET structure, comprising:
- providing a substrate;
- providing a semiconductor fin having a height and a width, wherein the height is at least five times greater than the width;
- providing a gate feature along a middle portion of the semiconductor fin, the gate feature having a first side and a second side;
- forming a first sacrificial doping layer on the semiconductor fin adjacent to and spaced from the first side of the semiconductor fin and a second sacrificial doping layer on the semiconductor fin adjacent to and spaced from the second side of the gate feature, wherein the first and second sacrificial doping layers are doped with a source/drain dopant material;
- heating the first and second sacrificial doping layers to cause some of the source/drain dopants to diffuse into the semiconductor fin; and
- applying an etchant to the first and second sacrificial doping layers.
15. The method of claim 14 further comprising:
- forming a sidewall spacer adjacent to the gate feature prior to forming the first and second sacrificial doping layers.
16. The method of claim 14 wherein the etchant is selective between the semiconductor fin and the first and second sacrificial doping layers.
17. The method of claim 14, wherein the step of forming the first and second sacrificial doping regions is further characterized as implanting the first and second sacrificial doping layers with the source/drain dopant material.
18. The method of claim 14 wherein the step of forming the first and second sacrificial doping layers is further characterized as depositing the first and second sacrificial doping layers in situ doped with the source/drain dopant material.
19. A method of forming a semiconductor device structure, comprising:
- forming a semiconductor feature having a height, width, and length protruding from a substrate, the semiconductor feature characterized as having a first side of the height and length on a first side of the width and a second side of the height and length on a second side of the width;
- forming a gate feature in a middle portion of the semiconductor feature on the first side, the second side, and the width, whereby a first source/drain extension region and a second source/drain extension region are uncovered by the gate feature;
- forming a sidewall spacer on the gate feature;
- forming a dopant-transferring material on the first and second source/drain extension regions;
- heating the dopant-transferring material; and
- substantially removing the dopant-transferring material.
20. The method of claim 19 wherein:
- the dopant-transferring material is doped by a selected one of the group consisting of implanting and in-situ doping;
- the sidewall spacer comprises a dielectric material; and
- the dopant-transferring material is characterized as being comprised of a different type of material than that of the semiconductor feature.
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Type: Grant
Filed: Jul 27, 2005
Date of Patent: Jan 29, 2008
Patent Publication Number: 20070026615
Assignee: Freescale Semiconductor, Inc. (Austin, TX)
Inventors: Sinan Goktepeli (Austin, TX), Voon-Yew Thean (Austin, TX)
Primary Examiner: Walter Lindsay, Jr.
Attorney: Robert L. King
Application Number: 11/190,411
International Classification: H01L 21/336 (20060101); H01L 21/338 (20060101);