Multiple die stack package
A semiconductor package, containing two or more stacked IC devices attached to a substrate. Each of the IC devices has a plurality of electrical contact regions which are connected to the substrate by means of electrical connections.
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The invention relates to a semiconductor package, specifically to a so-called Chip Scale Package (CSP).
The rapid growth of portable electronics and wireless communications apparatus has necessitated rapid development in the field of packaging semiconductor devices (also referred to as Integrated Circuits or ICs). A major area of development is the emergence of a class of new technology referred to as Chip Scale Packaging (CSP). The definition of CSP, as given by the Institute for Interconnecting and Packaging Electronic Circuits (IPC) refers to a package area which is less than 1.5 times that of the chip area. CSPs are especially used at present in memory IC devices. The intention is to maximise the capability and capacity of a device whilst minimising the package size. Thus the density of the package is increased.
A problem with this conventional packaging arrangement is that the scope for further reducing the ratio of the package area to the chip area is limited. There must always be some encapsulant 5, 25 around the periphery of the IC device 1, 21 to prevent accidental damage. Consequently the package area must be larger than the chip area. It is therefore an object of the present invention to provide a means for which the ratio of the package area to the chip area can be reduced.
According to the present invention, there is provided a semiconductor package comprising:
-
- a first IC device;
- a second IC device; and
- a substrate;
- wherein the first IC device is attached to the substrate and the second IC device is attached to the first IC device; the semiconductor package further comprising a first electrical connection between the first IC device and the substrate and a second electrical connection between the second IC device and the substrate.
This is advantageous since by packaging two IC devices in a single semiconductor package the ratio of the package area to the chip area may be significantly reduced and may even be brought below 1.0. The package size may be almost the same as in conventional packages (there may be some increase in the package height) but, using two memory chips for example, will yield a package with approximately double the memory density. Furthermore, this invention enables semiconductor packages to be produced which incorporate IC devices which perform different functions (for example processing and memory). Further, the likelihood of an IC device being produced that meets the required quality standard decreases as the size of the IC device increases (as the number of opportunities for error in the device increases). Consequently, it is cheaper to produce two devices of a given size than it is to produce a single device of twice the size (due to reduced wastage, for example). A package containing two IC devices, therefore, may have the same capacity and/or capability as a semiconductor package containing a single device, but it may be cheaper to produce and may have a smaller package area.
According to a further embodiment of the present invention, the substrate is attached to a first major face of the first IC device and the second IC device is attached to the second major face of the first IC device. He two IC devices therefore form a stack, with the result that the package area may be minimised to a little more than the area of one of the IC devices. This is advantageous as the ratio of the package area to the total IC device area may be reduced to between 0.5 and 1.0
Preferably, the substrate comprises one or more openings through which the first, and where required, additional electrical connections pass to connect electrical contact region(s) on the first IC device to the opposite side of the substrate than that to which the first IC device is attached.
The electrical contact regions may be arranged to be in convenient locations. Preferably, for example, the electrical contact regions may be arranged as a row in the centre of the side of the IC device that is attached to the substrate or may be located on mutually opposite edges of the face of the IC device attached to the substrate. This may be advantageous for arranging the layout of the signal transfer interface solder balls on the opposite side of the substrate.
Similarly the arrangement of the electrical contact regions on the second IC device may be varied but, preferably, they may be located in the centre or on mutually opposite edges of the face of the second IC device that is opposite to the face of the second IC device which is attached to the first IC device. This facilitates the establishment of electrical connections between the second IC device and the substrate.
Preferably, the semiconductor package contains at least a third IC device, the third IC device being attached to the second IC device by way of a spacer. Any subsequent IC devices may also attached by way of a spacer. The spacer ensures that each IC device does not interfere with the electrical contacts between other IC devices and the substrate. Adding additional IC devices is advantageous as it may multiply the advantages of the package containing two IC devices without necessarily substantially increasing the package areas.
In a preferred embodiment of the present invention, an electrical contact distribution element may be attached to one or more of the IC devices in the package. The electrical contact distribution element is used to provide an electrical contact between the electrical contact region on the relevant IC device and the electrical connection which is connected to the substrate. Such an element may be useful for reducing the complexity of attaching the electrical connections and ensuring that, especially in packages containing multiple IC devices, the electrical connections do not interfere with one another. The electrical contact distribution element may take the form of a wafer distribution layer, a substrate interposer, a dielectric interposer or a metallic interposer. Depending on the circumstances, each of these may be more convenient due to the ease of manufacture, the ease of assembling the element to the IC device, or the ease of attaching the electrical connections to it.
The invention will now be described by way of non-limiting examples with reference to the accompanying drawings in which:
In the figures, like parts have similar reference numerals.
The semiconductor package 60 shown in
In embodiments where the electrical distribution elements 76 are not integral to the IC device 73, the electrical contact region 74 may be connected to the electrical distribution elements 76 by means of electrical connections 77 such as those shown in
By the appropriate use of spacers and adhesive, any number of additional IC devices may be attached in this manner. Stacks of IC devices may be formed, for example, from pairs of IC devices, attached passive side to passive side and separated by spacers, or a plurality of IC devices, orientated the same way and each separated by spacers. Clearly, however, it may not be practical to add large numbers of IC devices due to restrictions on the electrical connections between the electrical contact regions on the IC devices and the electrical tracings on the substrate. A limit may also be reached on the number of solder balls that may be used to form the ultimate connections with the apparatus to which the semiconductor device is attached.
Although each of the exemplary semiconductor packages shown in
The adhesive used to attach the IC devices to the substrate and to one another may be in the form of an adhesive paste, coating or film. The electrical connections between the electrical contact regions and the substrate may be formed by a wire bond method or by a Tape Automatic Bonding (TAB) method. However the present invention is not limited to these methods. The electrical connections may be effected by any means capable of transferring signals between the IC device and the substrate. In addition, the first IC device may be coupled to the substrate by a flip chip method, which is well known in the art. The cover may be formed from a liquid encapsulant, that may be subsequently cured in an oven, or by a moulding process. Alternatively the cover may surround the semiconductor package but not encapsulate each of the components. Such a cover may, for example, be formed from glass, sealing the IC devices and connections from the environment.
Finally, although the embodiments shown in
The present disclosure relates to subject matter contained in priority Singapore Patent Application No. 200201096-5, filed on Feb. 21, 2002, the contents of which is herein expressly incorporated by reference in its entirety.
Claims
1. A semiconductor package comprising:
- a first IC device;
- a second IC device;
- a substrate, the first IC device being attached to the substrate and the second IC device being attached to the first IC device;
- a first electrical connection between the first IC device and the substrate;
- a second electrical connection between the second IC device and the substrate;
- an electrical contact distributor, attached to one of the first or second IC devices in the semiconductor package;
- wherein an electrical connection is connected to an associated electrical contact region with the electrical contact distributor; and
- wherein the electrical contact distributor comprises at least one of a wafer distribution layer; a substrate interposer; a dielectric interposer; and a metallic interposer;
- an opening, through the substrate, from a first side of the substrate to which the first IC device is attached, to a second side of the substrate opposite the first side; and
- an electrical contact region on the first IC device,
- wherein said first electrical connection passes through said opening and connects said electrical contact region on the first IC device to the second side of the substrate; and
- wherein said electrical contact region on the first IC device includes a row of electrical contact regions on the first IC device, said row located substantially centrally on a first side of the first IC device, to which the substrate is attached.
2. The semiconductor package according to claim 1, wherein the substrate is attached to a first major face of the first IC device and the second IC device is attached to a second major face of the first IC device.
3. A semiconductor package according to claim 1, wherein said electrical contact region on the first IC device is part of a first row of electrical contact regions on the first IC device; and the semiconductor package further comprises: a second opening through the substrate from the first side to the second side; a second row of electrical contact regions on the first IC device; and a third electrical connection, passing through said second opening and connecting an electrical contact region in said second row of electrical contact regions on the first IC device to the second side of the substrate.
4. A semiconductor package according to claim 3, wherein said first and second rows of electrical contact regions on the first IC device are located on mutually opposite edges of a first side of the first IC device, to which the substrate is attached.
5. The semiconductor package according to claim 1, further comprising an electrical contact region on the second IC device and said second electrical connection connects the electrical contact region on the second IC device to the substrate.
6. The semiconductor package according to claim 5, wherein said electrical contact region on the second IC device includes a first row of electrical contact regions on the second IC device; and the semiconductor package further comprises a second row of electrical contact regions on the second IC device and a third electrical connection that connects an electrical contact region in the second row of electrical contact regions on the second IC device to the substrate.
7. The semiconductor package according to claim 6, wherein said first and second rows of electrical contact regions on the second IC device are located on mutually opposite edges of a first side of the second IC device, which is on the other side of the second IC device to a second side, to which the first IC device is attached.
8. A semiconductor package according to claim 1, wherein said first electrical contact region on the second IC device is part of a row of electrical contact regions on the second IC device, said row located substantially centrally on a first side of the second IC device, which is on the other side of the second IC device to a second side, to which the first IC device is attached.
9. The semiconductor package according to claim 1, further comprising:
- at least a third IC device, the third IC device attached to the second IC device with a spacer; and
- at least one electrical connection that connects an electrical contact region on each of the IC devices to the substrate.
10. The semiconductor package according to claim 1, wherein the first IC device performs a different function than the second IC device.
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Type: Grant
Filed: Feb 11, 2003
Date of Patent: Oct 16, 2012
Patent Publication Number: 20030197284
Assignee: United Test & Assembly Center Limited (Singapore)
Inventors: Wang Chuen Khiang (Singapore), Koh Yong Chuan (Singapore), Fong Kok Chin (Singapore)
Primary Examiner: Michael Lebentritt
Attorney: Greenblum & Bernstein P.L.C.
Application Number: 10/361,814
International Classification: H01L 21/02 (20060101);