Integrated circuitry comprising nonvolatile memory cells having platelike electrode and ion conductive material layer

- Micron Technology, Inc.

An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.

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Description
TECHNICAL FIELD

Embodiments disclosed herein pertain to memory cells of integrated circuitry, and to methods of forming memory cells.

BACKGROUND

Memory is one type of integrated circuitry, and is used in computer systems for storing data. Such is usually fabricated in one or more arrays of individual memory cells. The memory cells might be volatile, semivolatile, or nonvolatile. Nonvolatile memory cells can store data for extended periods of time, in many instances including when the computer is turned off. Volatile memory dissipates and therefore requires to be refreshed/rewritten, in many instances multiple times per second. Regardless, the smallest unit in each array is termed as a memory cell and is configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

Integrated circuitry fabrication continues to strive to produce smaller and denser integrated circuits. Accordingly, the fewer components an individual circuit device has, the smaller the construction of the finished device can be. Likely the smallest and simplest memory cell will be comprised of two current conductive electrodes having a programmable material received there-between. The programmable material is selected or designed to be configured in a selected one of at least two different resistive states to enable storing of information by an individual memory cell. The reading of the cell comprises determination of which of the states the programmable material is in, and the writing of information to the cell comprises placing the programmable material in a predetermined resistive state. Some programmable materials retain a resistive state in the absence of refresh, and thus may be incorporated into nonvolatile memory cells.

One example memory device is a programmable metallization cell (PMC). Such may be alternatively referred to as conductive bridging RAM (CBRAM), nanobridge memory, or electrolyte memory. A PMC uses ion conductive material (for instance, a suitable chalcogenide or any of various suitable oxides) sandwiched between a pair of electrodes. A suitable voltage applied across the electrodes generates current conductive super-ionic clusters or filaments. Such result from ion transport through the ion conductive material which grows the clusters/filaments from one of the electrodes (the cathode), through the ion conductive material, and toward the other electrode (the anode). The clusters or filaments create current conductive paths between the electrodes. An opposite voltage applied across electrodes essentially reverses the process and thus removes the current conductive paths. A PMC thus comprises a high resistance state (corresponding to the state lacking a current conductive filament or clusters between the electrodes) and a low resistance state (corresponding to the state having a current conductive filament or clusters between the electrodes), with such states being reversibly interchangeable with one another.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a hybrid schematic and fragmentary structural view of a portion of an integrated circuit in accordance with an embodiment of the invention.

FIG. 2 is a sectional view of a portion of FIG. 1 taken through line 2-2 in FIG. 1.

FIG. 3 is a sectional view of a portion of FIG. 1 taken through line 3-3 in FIG. 1.

FIG. 4 is a sectional view of a portion of FIG. 1 taken through line 4-4 in FIG. 1.

FIG. 5 is a hybrid schematic and fragmentary structural view of a portion of an alternate embodiment integrated circuit in accordance with an aspect of the invention.

FIG. 6 is a diagrammatic sectional view of a substrate fragment in process in accordance with an embodiment of the invention.

FIG. 7 is a view of the FIG. 6 substrate at a processing step subsequent to that shown by FIG. 6.

FIG. 8 is a view of the FIG. 7 substrate, at 90° to the FIG. 7 cross section, at a processing step subsequent to that shown by FIG. 7.

FIG. 9 is a diagrammatic top-down view of the FIG. 8 substrate.

FIG. 10 is a view of the FIG. 8 substrate at a processing step subsequent to that shown by FIG. 8.

 DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention encompass integrated circuitry comprising a nonvolatile memory cell, and methods of forming a nonvolatile memory cell. Referring initially to FIGS. 1-4, an example integrated circuit 10 comprises a plurality of nonvolatile memory cells 14 formed within a memory array 12. An individual memory cell 14 comprises a first current conductive electrode 16, a second current conductive electrode 18 formed elevationally outward thereof, and an ion conductive material 20 received between such electrodes. A material 22, which may be homogenous or non-homogenous, may surround components 16, 18 and 20. Material 22 is not shown in FIG. 1 for clarity in depicting the operable components. Material 22 would likely be insulative at least where contacting components 16, 18, and 20 in the figures, with doped silicon dioxide being an example.

Components 16, 18, 20 and material 22 may be fabricated relative to or supported by a suitable base substrate (not shown), for example a semiconductor substrate which may comprise monocrystalline silicon and/or other semiconductive material. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above.

Electrodes 16 and 18 may comprise any suitable current conductive material, and may be homogenous or non-homogenous. In the context of this document, “current conductive material” is a composition where electric current flow would inherently occur therein predominantly by movement of subatomic positive and/or negative charges when such are generated as opposed to predominantly by movement of ions. At least one of first electrode 16 and second electrode 18 has an electrochemically active surface received directly against ion conductive material 20. In this document, a material or structure is “directly against” another when there is at least some physical touching contact of the stated materials or structures relative one another. In contrast, “over” encompasses “directly against” as well as constructions where intervening material(s) or structure(s) result in no physical touching contact of the stated materials or structures relative one another. By way of examples only, suitable current conductive and electrochemically active materials include copper, silver, and alloys including at least one of copper and silver. Example suitable current conductive and electrochemically inactive materials include titanium nitride, gold, tungsten, platinum, and alloys including at least one of gold, tungsten or platinum.

Ion conductive material 20 may be a solid, gel, or any other suitable phase, and may be homogenous or non-homogenous. Example suitable materials comprise chalcogenide-type (for instance, materials comprising one or more of germanium, selenium, antimony, tellurium, sulfur, copper, etc.; with example chalcogenide-type materials being Ge2Sb2Te5, GeS2, GeSe2, CuS2, and CuTe) and/or oxides such as zirconium oxide, hafnium oxide, tungsten oxide, silicon oxide (specifically, silicon dioxide), gadolinium oxide, etc. Such may have silver ions or other suitable ions diffused therein for ionic conduction, analogously to structures disclosed in U.S. Pat. No. 7,405,967 and U.S. Patent Publication Number 2010/0193758.

In one embodiment, second electrode 18 may be considered as having a lateral outermost sidewall 21 (FIGS. 2 and 3) and ion conductive material 20 may be considered as having a transverse outermost sidewall 24 (FIG. 2) received directly against such second electrode sidewall 21. In one embodiment, such may be vertically oriented at least where each is directly received against the other. In this document, vertical is a direction generally orthogonal to a primary surface relative to which the substrate is processed during fabrication and which may be considered to define a generally horizontal direction. Further, “vertical” and “horizontal” as used herein are general perpendicular directions relative one another independent of orientation of the substrate in three dimensional space. Further in this document, “elevationally outward” is with reference to the vertical direction from a base substrate upon which the circuitry is fabricated.

In one embodiment, first electrode 16 may extend laterally in a first direction 26 and ion conductive material 20 may extend laterally in a second direction 28 different from and intersecting first direction 26. Accordingly, such angle relative to one another, with reference to “angle” herein meaning any angle other than the straight angle. In one embodiment, first and second directions 26, 28 intersect at an angle from about 45° to 90°, and in one embodiment from 80° to 90°. Such are shown in FIGS. 1-4 as intersecting at a 90° angle 29 (FIG. 4), as an example. First direction 26 and direction 28 may be parallel to the horizontal direction.

Regardless and referring to FIG. 4, in one embodiment ion conductive material 20 and first electrode 16 may be considered as contacting one another at a maximum contacting area 30. Such is defined by a transverse thickness 32 of ion conductive material 20 and a transverse thickness 34 of first electrode 16 where such cross at angle 29 of intersecting directions 26 and 28. Such may provide an advantage of more precisely defining a position from where a conduction channel through material 20 will initiate upon programming to a low resistance state. Such may also provide an advantage of assuring formation of only a single conduction channel, where such is desired. In one embodiment, at least one of first electrode 16 and ion conductive material 20 has its respective transverse thickness where such cross which is less than F, where F is a minimum feature dimension of lithographically-defined features of the substrate (meaning the minimum of all feature dimensions which are defined lithographically). Regardless, an example thickness range 32 for ion conductive material 20 is from about 2 to 30 nanometers, while that for first electrode 16 is from about 2 to 20 nanometers (thickness 34). In one embodiment, each of the first electrode 16 and ion conductive material 20 has a respective uniform transverse thickness which may be the same or different from each other, with different thicknesses being shown.

First electrode 16 may be considered as having an elevationally outer surface 36 with, in one embodiment, at least a portion thereof being received directly against ion conductive material 20. Analogously, second electrode sidewall 21 may be considered as comprising a surface received directly against ion conductive material 20. At least a portion of at least one of sidewall 21 or surface 36 as received directly against ion conductive material 20 is electrochemically active. Accordingly, second electrode 18 and/or first electrode 16 has some electrochemically active surface received directly against ion conductive material 20.

In one embodiment, at least second electrode 18 comprises an electrochemically active surface. By way of example, second electrode 18 is shown as comprising a composite of current conductive material 40 and current conductive material 42, with material 42 in one embodiment also constituting an electrochemically active material having a surface 21 which is received directly against ion conductive material 20. Material 40 and material 42 may, respectively, be homogenous or non-homogenous. An example thickness range for current conductive and electrochemically active material 42 is from about 2 to 30 nanometers, while that for current conductive material 40 is from about 10 to 80 nanometers. Current conductive material 40 may or may not also be electrochemically active, and in one embodiment is electrochemically inactive, for example comprising elemental tungsten. In one embodiment, the current conductive material of first electrode 16 may be electrochemically inactive, again with elemental tungsten being one specific example.

Within array 12, material 42 and/or material 40 may extend/run continuously in individual of the column/row lines, or first electrode 16 may run continuously in individual of the column/row lines. Regardless, ion conductive material 20 may extend/run continuously in a line, may be continuous throughout the array, or may be patterned with defined edges for individual of the memory cells. As an example only, FIGS. 1-4 show material 40 and ion conductive material 20 extending along or as respective continuous lines, with material 42 and first electrode 16 being isolated structures for each memory cell 14.

In one embodiment where at least the second electrode comprises an electrochemically active material having a surface directly against ion conductive material, the ion conductive material has an elevationally outermost surface which is elevationally outward of an elevationally outermost surface of the electrochemically active material. For example in the embodiment of FIGS. 1-4, electrochemically active material 42 may be considered as having an elevationally outermost surface 46 and ion conductive material 20 may be considered as having an elevationally outermost surface 48. Surface 48 is elevationally outward of surface 46. In one embodiment, the second electrode may comprise an electrochemically inactive material which is received elevationally outward of the electrochemically active material of the second electrode. The electrochemically inactive material comprises an elevationally outermost surface which is elevationally coincident with the elevationally outermost surface of the ion conductive material. For example in the embodiment of FIGS. 1-4 where material 42 is electrochemically active and material 40 is electrochemically inactive, material 40 comprises an elevationally outermost surface 50 which is elevationally coincident with surface 48 of ion conductive material 20.

In one embodiment, each of the first electrode, the second electrode, and the ion conductive material is platelike and oriented perpendicularly relative each other. In the context of this document, “platelike” defines a construction having length and width dimensions which are each at least 2.5 times greater than a maximum transverse thickness/depth of the construction orthogonal to the length and width. FIG. 1 depicts such a construction where each of electrodes 16, 18 and ion conductive material 20 is platelike (having edge surfaces) and perpendicularly oriented relative to each other. Any other attribute may apply as described above. By way of example, the second platelike electrode may comprise an electrochemically active surface received directly against the platelike ion conductive material. Further as an example, the platelike ion conductive material may comprise an elevationally outermost surface having the second electrode received directly there-against, for example as shown in the embodiment of FIG. 5. The electrodes and ion conductive material of the embodiments of FIGS. 1 and 5 may be considered respectively as being platelike in a volume expanse encompassing an individual memory cell 14/14a even if one or more of such extends or runs continuously in an individual line or is otherwise continuous in some aspect other than shown.

FIGS. 2 and 3 diagrammatically depict memory cell 14 as being programmed in an example low resistance “1” state wherein a low electrical resistance/current conduction path 44 has been formed through ion conductive material 20. Conduction path 44 extends from and between surface 36 of first electrode 16 and sidewall 21 of current conductive material 42 where such are each received directly against ion conductive material 20. Conduction path 44 may be in the form of a path of current conductive particles which may or may not be directly against one another, with single ions and super-ionic clusters being examples. In some embodiments, the conduction path may be a filament, for example as described in U.S. Patent Publication No. 2010/01100759. Conduction path 44 may be formed by application of a suitable electric field through ion conductive material 20 to cause ions from the electrochemically active surface of one electrode to pass towards the opposing electrode and grow conduction path 44 through ion conductive material 20 from such opposing electrode. Such may be achieved by providing a suitable voltage differential to electrodes 16 and 18. Memory cell 14 may be programmed to an example high resistance “0” state by at least reversing polarity of the voltage differential to reverse the process, thereby removing conduction path 44. Memory cell 14 may thereby be repeatedly programmable between at least two programmed states by application of suitable voltage differentials to move between programmed states.

FIG. 1 depicts but one example architecture for array 12 of integrated circuit 10. In such, memory cell 14 is connected between or as portions of a schematically illustrated field effect transistor 100 and a schematically illustrated data/sense line 102 (i.e., a bit line). First electrode 16 is connected with or comprises one source/drain region of transistor 100, with the other source/drain region thereof connected to a suitable potential depicted as ground in FIG. 1, as an example. The gate of field effect transistor 100 may comprise a control line 104 (i.e., a word line) of a row line or column line of memory cells 14. Bit line 102 may comprise a corresponding other of a row line or column line of memory cells 14.

Some or all of second electrodes 18 in an individual data/sense line 102 may extend continuously along such data/sense line. As an example alternate embodiment, the architecture may be reversed. For example, some or all of first electrodes 16 may extend continuously along an individual control line, and individual second electrodes 18 may be isolated constructions relative one another along a corresponding data/sense line. Further and regardless, the roles of data/sense and control lines may be reversed.

An alternate embodiment nonvolatile memory cell 14a is shown in FIG. 5 in comparison to a single memory cell 14 in FIG. 1. Like numerals from the above-described memory cell 14 are used where appropriate, with some construction differences being indicated with the suffix “a”. In memory cell 14a, second electrode 18a is received directly against elevationally outermost surface 48 of ion conductive material 20. Any other attribute as described above may apply to the nonvolatile memory cell construction 14a of FIG. 5. As an alternate example, in one embodiment, second electrode 18/18a might be oriented edgewise (not shown) such that it is oriented like first electrode 16, for example any of directly over and parallel thereto, not directly over and parallel thereto, and directly over or not directly over yet angled relative to first electrode 16.

Embodiments of the invention encompass methods of forming a nonvolatile memory cell. Example such methods are described with reference to FIGS. 6-10 with respect to a substrate fragment 60 in fabrication of a nonvolatile memory cell of the FIGS. 1-4 embodiments. The artisan will appreciate that the FIG. 5 or other nonvolatile memory cells may also or alternately be fabricated. Further and regardless, the fabrication methods disclosed herein are not necessarily limited by the structural aspects described above, nor are any structural aspects described above necessarily limited by methods of fabrication, unless so claimed.

Referring to FIG. 6, substrate 60 may comprise a semiconductor substrate, and is shown as comprising a material 62 having a first sidewall 64. Material 62 may be of any composition, may be homogenous or non-homogenous, and sidewall 64 may be vertically oriented. An example material 62 is some portion of material 22 of the above-described embodiments.

Referring to FIG. 7, a first current conductive electrode material 66 has been formed over first sidewall 64. In one embodiment, material 66 is formed to have a transverse thickness (thickness orthogonal to sidewall 64) which is less than F. An example technique for forming material 66 is by any suitable conformal deposition of material 66 over material 62, followed by anisotropic etching thereof to clear material 66 from the outer surfaces of material 62. Such may be conducted with or without masking. Regardless, alternate or additional techniques may be used. First current conductive electrode material 66 may have any of the attributes, including but not limited to “shape”, of first electrode 16 described above. Accordingly, first current conductive electrode material 66 may be first electrode 16 of the FIGS. 1-4 embodiment.

Referring to FIGS. 8 and 9, a second sidewall 68 has been formed elevationally outward of first current conductive material material 66, and first and second sidewalls 64, 68 have been formed at an angle 65 relative one another. In one embodiment, such angle is from about 45° to 90°, in one embodiment from 80° to 90°, and with an angle of 90° being shown. Sidewall 68 may be vertically oriented. In the embodiment of FIGS. 8 and 9, a material 63 has been formed over material 62 and first current conductive electrode material 66 and second current conductive electrode 18 have been provided relative thereto. Material 63 may be of the same composition as material 62. Materials 62 and 63 might be considered as a composite of material 22 of the embodiments of FIGS. 1-4.

Referring to FIG. 10, an ion conductive material 70 has been formed over second sidewall 68 and directly against an elevationally outer surface 36 of first current conductive material 66. Example materials and attributes are as described above with respect to ion conductive material 20. Accordingly, ion conductive material 70 may be ion conductive material 20 in the first described embodiments. An example technique for forming ion conductive material 70 is by any suitable conformal deposition of material 70 over materials 40, 63, and 62, followed by anisotropic etching thereof to clear material 70 from the outer surfaces of materials 40, 63, and 62. Ion conductive material 70 and first current conductive material 66 contact one another at a maximum contacting area defined by a transverse thickness of the ion conductive material and a transverse thickness of the first current conductive electrode where such cross at their angle of intersection, for example analogous to and as depicted and described above with respect to FIG. 4.

Regardless, a second current conductive electrode is provided directly against the ion conductive material, with at least one of the first current conductive electrode and the second current conductive electrode having an electrochemically active surface directly against the ion conductive material. The second electrode may have any of the attributes as described above. Further, the ion conductive material may be formed before or after forming the second current conductive electrode. The FIGS. 6-10 embodiment is an example wherein the ion conductive material is formed after forming the second current conductive electrode. Alternately by way of example, FIG. 5 depicts an embodiment more conducive to forming the ion conductive material before forming the second current conductive electrode.

An embodiment of the invention includes a method of forming a nonvolatile memory cell comprising forming first and second electrodes where at least one of such has an electrochemically active surface, and independent of any other attribute described above (although such are example attributes which may be used in this embodiment). For example, such formation of first and second electrodes in accordance with this embodiment is independent of elevational or other orientation of the electrodes relative to each other. Regardless, after forming the first and second electrodes, an ion conductive material is deposited directly against the electrochemically active surface. Heretofore, the prior art is not understood to anywhere deposit an ion conductive material directly against an electrochemically active surface of a first and/or second electrode after both such electrodes have been formed.

In one embodiment, a dielectric may be provided between the first and second electrodes, and have a lateral sidewall. The ion conductive material may also be deposited directly against the dielectric lateral sidewall. For example with respect to FIG. 8 where material 63 comprises a dielectric, a portion of sidewall 68 (i.e., that which is below material 42) is a dielectric lateral sidewall directly against which ion conductive material 70 is deposited, for example as shown in FIG. 10. Any other attribute may be used as described above.

In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated circuit comprising a nonvolatile memory cell, the nonvolatile memory cell comprising:

a first electrode, a second electrode, and an ion conductive material between the first and second electrodes; the second electrode having an electrochemically active surface directly against the ion conductive material and an electrochemically inactive surface directly against the ion conductive material; the second electrode being elevationally outward of the first electrode;
the first electrode extending laterally in a first direction, the ion conductive material extending laterally in a second direction different from and intersecting the first direction, the first electrode being directly against the ion conductive material only where the first and second directions intersect, the second electrode having a lateral outermost sidewall and the ion conductive material having a transverse outermost sidewall directly against the second electrode lateral outermost sidewall, the second electrode being directly against the ion conductive material only at the transverse outermost sidewall of the ion conductive material; and
the first electrode being platelike and having an elevational thickness which is greater than thinnest transverse thickness of the first electrode, the first platelike electrode having an elevationally outermost surface; the ion conductive material being platelike and having an elevational thickness which is greater than thinnest transverse thickness of the ion conductive material, the platelike ion conductive material having an elevationally innermost surface that is directly against the elevationally outermost surface of the first platelike electrode; the first platelike electrode and the platelike ion conductive material intersecting at an angle relative one another.

2. The integrated circuit of claim 1 wherein the lateral outermost sidewall and the transverse outermost sidewall are vertically oriented.

3. The integrated circuit of claim 1 wherein at least one of the first electrode and the ion conductive material has its thinnest transverse thickness where received directly against the other of the first electrode or ion conductive material which is less than F, where F is a minimum feature dimension of lithographically-defined features.

4. The integrated circuit of claim 1 wherein each of the first electrode and the ion conductive material has its thinnest transverse thickness where received directly against the other of the first electrode or ion conductive material which is less than F, where F is a minimum feature dimension of lithographically-defined features.

5. An integrated circuit comprising a nonvolatile memory cell, the nonvolatile memory cell comprising:

a first electrode, a second electrode, and an ion conductive material between the first and second electrodes; the second electrode having an electrochemically active surface directly against the ion conductive material and an electrochemically inactive surface directly against the ion conductive material; the second electrode being elevationally outward of the first electrode;
the first electrode extending laterally in a first direction, the ion conductive material extending laterally in a second direction different from and intersecting the first direction, the first electrode being directly against the ion conductive material only where the first and second directions intersect, the first and second directions intersecting at an angle from 45° to less than 90°; and
the first electrode being platelike and having an elevational thickness which is greater than thinnest transverse thickness of the first electrode, the first platelike electrode having an elevationally outermost surface; the ion conductive material being platelike and having an elevational thickness which is greater than thinnest transverse thickness of the ion conductive material, the platelike ion conductive material having an elevationally innermost surface that is directly against the elevationally outermost surface of the first platelike electrode.

6. The integrated circuit of claim 1 wherein the second electrode is platelike.

7. An integrated circuit comprising a nonvolatile memory cell, the nonvolatile memory cell comprising:

a first electrode, a second electrode, and an ion conductive material between the first and second electrodes; the second electrode having an electrochemically active surface directly against the ion conductive material and an electrochemically inactive surface directly against the ion conductive material; the second electrode being elevationally outward of the first electrode;
the first electrode extending laterally in a first direction, the ion conductive material extending laterally in a second direction different from and intersecting the first direction, the first electrode being directly against the ion conductive material only where the first and second directions intersect, each of the first electrode and the ion conductive material being platelike and intersecting at an angle other than 90°; and
the first electrode being platelike and having an elevational thickness which is greater than thinnest transverse thickness of the first electrode, the first platelike electrode having an elevationally outermost surface; the ion conductive material being platelike and having an elevational thickness which is greater than thinnest transverse thickness of the ion conductive material, the platelike ion conductive material having an elevationally innermost surface that is directly against the elevationally outermost surface of the first platelike electrode.

8. The integrated circuit of claim 1 comprising a plurality of said nonvolatile memory cells within a memory array.

9. An integrated circuit comprising a nonvolatile memory cell, the nonvolatile memory cell comprising:

a first platelike electrode, a second platelike electrode, and a platelike ion conductive material between the first and second platelike electrodes; the second platelike electrode having an electrochemically active surface directly against the platelike ion conductive material and an electrochemically inactive surface directly against the ion conductive material; the second platelike electrode being elevationally outward of the first platelike electrode; and
the first platelike electrode having an elevational thickness which is greater than thinnest transverse thickness of the first electrode, the first platelike electrode having an elevationally outermost surface; the platelike ion conductive material having an elevational thickness which is greater than thinnest transverse thickness of the ion conductive material, the platelike ion conductive material having an elevationally innermost surface that is directly against the elevationally outermost surface of the first platelike electrode; the first platelike electrode and the platelike ion conductive material intersecting at an angle relative one another.

10. An integrated circuit comprising a nonvolatile memory cell, the nonvolatile memory cell comprising:

a first platelike electrode, a second platelike electrode, and a platelike ion conductive material between the first and second platelike electrodes; the second platelike electrode having an electrochemically active surface directly against the platelike ion conductive material and an electrochemically inactive surface directly against the ion conductive material; the second platelike electrode being elevationally outward of the first platelike electrode;
the platelike ion conductive material being oriented perpendicularly relative to the first platelike electrode, the second platelike electrode being oriented perpendicularly relative to the plate like ion conductive material, the second platelike electrode being oriented perpendicularly relative to the first platelike electrode;
the first platelike electrode having an elevational thickness which is greater than thinnest transverse thickness of the first electrode, the first platelike electrode having an elevationally outermost surface; the platelike ion conductive material having an elevational thickness which is greater than thinnest transverse thickness of the ion conductive material, the platelike ion conductive material having an elevationally innermost surface that is directly against the elevationally outermost surface of the first platelike electrode;
the second platelike electrode comprising an electrochemically active material having an elevationally outermost surface that is not received against the platelike ion conductive material; and
the ion conductive material having an elevationally outermost surface which is elevationally outward of the elevationally outermost surface of the electrochemically active material of the second platelike electrode.

11. The integrated circuit of claim 9 wherein each of the first platelike electrode and platelike ion conductive material is of a respective uniform transverse thickness.

12. The integrated circuit of claim 9 wherein each of the first platelike electrode and the platelike ion conductive material are of a respective uniform transverse thickness which is less than F, where F is a minimum feature dimension of lithographically-defined features.

13. The integrated circuit of claim 9 wherein the elevationally outermost surface of the first platelike electrode has a minimum cross dimension equal to the thinnest transverse thickness of the first platelike electrode.

14. The integrated circuit of claim 9 wherein the elevationally innermost surface of the ion conductive material has a minimum cross dimension equal to the thinnest transverse thickness of the ion conductive material.

15. The integrated circuit of claim 9 wherein,

the elevationally outermost surface of the first platelike electrode has a minimum cross dimension equal to the thinnest transverse thickness of the first platelike electrode; and
the elevationally innermost surface of the ion conductive material has a minimum cross dimension equal to the thinnest transverse thickness of the ion conductive material.
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Patent History
Patent number: 8759809
Type: Grant
Filed: Oct 21, 2010
Date of Patent: Jun 24, 2014
Patent Publication Number: 20120097913
Assignee: Micron Technology, Inc. (Boise, ID)
Inventors: Jun Liu (Boise, ID), John K. Zahurak (Boise, ID)
Primary Examiner: William F Kraig
Assistant Examiner: Khaja Ahmad
Application Number: 12/909,650