Well-tap structures for analog matching transistor arrays
In one embodiment, an integrated circuit includes an array of active structures, an array of dummy structures and multiple well-tap structures. The array of dummy structures surrounds the array of active structures. The well-tap structures may be interposed between the array of active structures and the array of dummy structures. In one embodiment, each of the well-tap structures may include a well, a diffusion region and a gate-like structure. The well may be formed in a substrate and is of a first doping type. The diffusion region may be formed in the well and is also of the first doping type. The gate-like structure may be formed above the substrate and adjacent to the diffusion region.
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Generally, an integrated circuit device such as a programmable logic device (PLD) may include digital and analog circuits. Examples of analog circuits include transceiver circuitry, voltage supply circuitry, filter circuitry, and mirroring circuits. Examples of digital circuits include programmable logic circuits and memory circuits.
A high-precision current mirror circuit, which generates an electrical current that is equal to a reference electrical current, may require matched active structures (e.g., transistor structures). Using a large number of dummy arrays may help to reduce manufacturing variations between the active structures so that a high-precision current mirror circuit may be formed. However, having a high number of dummy arrays may not be compatible with the latch-up rule (a design-for-manufacturing (DFM) requirement) for the active structures in the semiconductor circuit. The latch-up rule requires a well-tap structure to be formed within a relatively short distance (i.e., within 30 microns) from the active structures.
Although there are solutions to form a high-precision current mirror circuit such as placing well-tap structures between every two rows/columns of the active structures in the analog circuits, such solutions may generally increase the overall size of the integrated circuit and as such, are not preferable.
SUMMARYEmbodiments described herein relate to well-tap structures within an integrated circuit. It should be appreciated that the embodiments can be implemented in numerous ways, such as a process, an apparatus, a system, a device, or a method. Several embodiments are described below.
In one embodiment, an integrated circuit includes an array of active structures, an array of dummy structures, and multiple well-tap structures. The array of dummy structures may surround the array of active structures. The well-tap structures may be interposed between the array of active structures and the array of dummy structures. Each of the well-tap structures may include a well, a diffusion region, and a gate-like structure. The well may be formed in a substrate and is of a first doping type. The diffusion region may be formed in the well and is also of the first doping type. The gate-like structure may be formed above the substrate and adjacent to the diffusion region.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
The following embodiments describe a well-tap structure within an integrated circuit. It will be obvious, to one skilled in the art, that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present embodiments.
In one embodiment, integrated circuit device 100 may be an application specific integrated circuit (ASIC) device, an application standard specific product (ASSP) device, a programmable logic device (PLD) or a microprocessor device. In general, ASIC and ASSP devices may perform fixed and dedicated functions. PLD devices may be programmable to perform a variety of functions. An example of a PLD device may be a field programmable gate array (FPGA) device. Microprocessor devices, coupled together with other devices (e.g., a memory device), may be utilized to perform instructions provided by programming code.
Integrated circuit device 100 may be used in different types of communication systems, such as wireless systems, wired systems, etc. In one embodiment, integrated circuit device 100 may be a PLD that is utilized for controlling data transfer between different devices, for example, microprocessor devices and memory devices. Hence, integrated circuit device 100 may include circuits that may be used to implement various transmission standards that allow integrated circuit device 100 to communicate with external devices such as memory devices (not shown) that may be coupled to integrated circuit device 100.
Referring still to
It should be appreciated that logic circuitry 110 may be utilized for performing core functions of integrated circuit device 100. Therefore, logic circuitry 110 may include specific circuitry for the functions that define integrated circuit device 100. For example, logic circuitry 110 may include circuits that perform memory device addressing and processing of information retrieved from a memory device when integrated circuit device 100 is used as a memory controller. In another example, logic circuitry 110 may include programmable logic elements when integrated circuit device 100 is a PLD. The programmable logic elements may further include circuits such as look-up table circuitry, multiplexers, product-term logic, registers, memory and the like. The programmable logic elements may be programmed by a user (e.g., a designer or an engineer) to perform any desired function. It should be appreciated that logic circuitry 110 may mainly include digital circuits (e.g., logic gates, registers, etc.).
Transceivers 120 and I/O circuits 130 may be utilized for transferring signals in or out of integrated circuit device 100. For example, signals from logic circuitry 110 may be transferred out of integrated circuit device 100 through one of the transceivers 120 or I/O circuits 130. Additionally, signals received from an external device (external to integrated circuit device 100) may be transferred to logic circuitry 110 through one of the transceivers 120 or I/O circuits 130. In one embodiment, both transceivers 120 and I/O circuits 130 may be considered as external interfacing circuitry of integrated circuit device 100. Signals may accordingly be transferred out or received by one of the transceivers 120 and I/O circuits 130 through its signal pin (not shown). Each transceiver 120 may include a transmitter circuit and a receiver circuit. Alternatively, each I/O circuit 130 may include only an input circuit or an output circuit.
Power circuits 140 may be utilized to maintain a constant voltage supply within integrated circuit device 100. In one embodiment, power circuits 140 may include voltage regulator circuits that may provide constant voltage signals to the respective circuits within integrated circuit device 100. As shown in the embodiment of
Transceivers 120, I/O circuits 130 and power circuits 140 may include analog circuits (e.g., current mirror circuits, amplifier circuits, etc.). The analog circuits within transceivers 120, I/O circuit 130 and power circuits 140 may include matched active circuits (e.g., circuits including matching transistors). These circuits may also be required to satisfy latch-up rules. The latch-up rules may vary depending on the type of semiconductor process that is being utilized. In one embodiment, the latch-up rules may require a well-tap structure to be formed within a relatively short distance (e.g., 30 microns (μm)) from an active structure that forms any one of transceivers 120, I/O circuits 130 or power circuits 140.
Current mirror circuit 200 may be utilized to copy electric current from one branch (which may include terminal 240 and transistor 210) to another branch (which may include transistor 220). As shown in the embodiment of
It should be appreciated that there are multiple topologies for current mirror circuit 200. In one exemplary embodiment, current mirror circuit 200 may be a Widlar current mirror circuit. Alternatively, current mirror circuit 200 may be a Wilson current mirror circuit. Each topology may provide different basic characteristics (e.g., output impedance, bandwidth, etc.).
Transistors 210 and 220 may be formed using multiple smaller-sized transistors. Transistors 210 and 220 has to be identical in terms of their physical dimensions (i.e., width, length and height) and doping concentration levels in order to generate a high-precision current mirror circuit (i.e., IOUT=IREF). Therefore, the smaller-sized transistors that collectively formed transistors 210 and 220 may need to be identical to each other. In one embodiment, the identical smaller-sized transistors may be formed when a layout as shown in embodiment of
Transistors 210 and 220 may be complementary metal oxide semiconductor (CMOS) transistors. In the embodiment of
Circuit 310 may include active region 320, dummy region 340 and well-tap rows 330. In
As shown in the embodiment of
In
Dummy structures 341 may be formed for the purpose of design-for-manufacturing. In one embodiment, dummy structures 341 may reduce the impact of undesired manufacturing process variations (e.g., variations in the process of manufacturing the polycrystalline structures or the oxide diffusion regions). Reduced manufacturing process variations may help to form identical active structures 321. Therefore, a large array of dummy structures 341 may couple active structures 321, as shown in the embodiment of
In one embodiment, dummy region 340 encompasses a width of at least 50 micrometers away from an edge of active region 320. It should be appreciated that dummy structures 341 may be dummy transistors when active structures 321 are transistor structures. Similar to active structures 321, dummy structures 341 may be formed using the oxide diffusion regions and the polycrystalline structures. The size of the polycrystalline structure and the oxide diffusion regions that form each dummy structure 341 may be identical to that of the polycrystalline structure and oxide diffusion regions that form each active structure 321 and may therefore sometimes be referred to as non-functional transistor structures.
Well-tap structures 331 may be needed to provide a substrate voltage for active structures 321. Well-tap structures 331 may be utilized to prevent a latch-up for analog circuit 310. Latch-up occurs when there is an inadvertent creation of a short circuit between the power supply rails of an active structure 321, which results in a large amount of current to flow through a parasitic structure which disrupts proper functioning of the part, and can oftentimes permanently damage the active structures and any surrounding circuitry. According to a particular wafer fabrication semiconductor design rule, well-tap region 330 has to be placed less than 30 micrometers from the center of active region 320. In one embodiment, a well-tap structure (e.g., well-tap structure 331) may be interposed between an active region (e.g., active region 320) and a dummy region (e.g., dummy region 340). Well-tap structures 331 may be N-type well-tap structures (as shown in
Similar to active structures 321 and dummy structures 341, well-tap structures may be formed using the oxide diffusion regions and the polycrystalline structures. In addition to that, the size of the polycrystalline structure and the oxide diffusion regions that form each well-tap structure 331 may be identical to that of the polycrystalline structure and oxide diffusion regions that form each active structure 321 or each dummy structure 341.
As shown in the embodiment of
In one embodiment, N-well 450 may be formed on a P-type substrate (not shown). The two N+ type diffusion regions 410 and 420 are formed within N-well 450. However, the N+ type diffusion regions 410 and 420 may have a higher doping concentration than N-well 450. Each N+ type diffusion region may be coupled to a voltage supply source (VDD). Polycrystalline structure 440 is formed above N-well 450 and on top of oxide layer 430. As shown in the embodiment of
In one embodiment, P-well 550 may be formed on an N-type substrate. The two P+ type diffusion regions 510 and 520 are formed within P-well 550. However, the P+ type diffusion regions 510 and 520 may have a higher doping concentration than P-well 550. Each P+ type diffusion region may be coupled to a ground source (VSS). Polycrystalline structure 540 is formed above P-well 550 and on top of oxide layer 530. As shown in the embodiment of
As shown in the embodiment of
Well-tap structure 610 is an N-type well-tap structure. Similar to active structure 620, well-tap structure 610 includes two diffusion regions and a polycrystalline structure. The two diffusion regions include a high concentration of N-type dopants (as reflected by N+). The polycrystalline structure is also doped with a high concentration of N-type dopants. As shown in the embodiment of
Dummy structure 630 may be similar to well-tap structure 610. However, as shown in the embodiment of
As shown in the embodiment of
Well-tap structure 710 is a P-type well-tap structure. Similar to active structure 720, well-tap structure 710 includes two diffusion regions and a polycrystalline structure. The two diffusion regions include a high concentration of P-type dopants (as reflected by P+). The polycrystalline structure is also doped with a high concentration of P-type dopants. As shown in the embodiment of
Dummy structure 730 may be similar to active structure 710. However, as shown in the embodiment of
At step 810, diffusion regions for active structures, dummy structures and well-tap structures are formed. In one exemplary embodiment, when the active structure is a PMOS transistor, the diffusion regions for the active structures, the dummy structures and the well-tap structures may be similar to the P+ type diffusion regions for active structure 620, the P+ type diffusion regions for dummy structure 630 and the N+ type diffusion regions for well-tap structure 610, respectively, of
At step 820, polycrystalline structures for the active structures, the dummy structures and the well-tap structures are formed. When the active structures include PMOS transistors, the polycrystalline structures for the active structures, the dummy structures and the well-tap structures may be similar to the P+ polycrystalline structure for active structure 620, the P+ polycrystalline structure for dummy structure 630 and the N+ polycrystalline structure for well-tap structure 610, respectively, of
At step 830, the diffusion regions for the active structures, the dummy structures and the well-tap are coupled to their respective terminals. For example, when the active structure is a PMOS transistor, the diffusion regions for the active structure may be coupled terminals that transmit signals (e.g., similar to the diffusion regions for active structure 620 of
In addition to that, the polycrystalline structures for the active structures, the dummy structures and the well-tap may also be coupled to their respective voltage terminals. For example, the polycrystalline structure for the active structure may be coupled to a terminal that transmits a control signal, whereas the polycrystalline structures for the dummy structure and the well-tap structure may be coupled to a VDD voltage level and a VSS voltage level, respectively (as shown by dummy structure 630 and well-tap structure 610 of
The embodiments thus far have been described with respect to integrated circuits. The methods and apparatuses described herein may be incorporated into any suitable circuit. For example, they may be incorporated into numerous types of devices such as programmable logic devices, application specific standard products (ASSPs), and application specific integrated circuits (ASICs). Examples of programmable logic devices include programmable arrays logic (PALs), programmable logic arrays (PLAs), field programmable logic arrays (FPLAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), just to name a few.
The programmable logic device described in one or more embodiments herein may be part of a data processing system that includes one or more of the following components: a processor; memory; IO circuitry; and peripheral devices. The data processing can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application where the advantage of using programmable or re-programmable logic is desirable. The programmable logic device can be used to perform a variety of different logic functions. For example, the programmable logic device can be configured as a processor or controller that works in cooperation with a system processor. The programmable logic device may also be used as an arbiter for arbitrating access to a shared resource in the data processing system. In yet another example, the programmable logic device can be configured as an interface between a processor and one of the other components in the system. In one embodiment, the programmable logic device may be one of the family of devices owned by ALTERA Corporation.
Although the methods of operations were described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or described operations may be distributed in a system which allows occurrence of the processing operations at various intervals associated with the processing, as long as the processing of the overlay operations are performed in a desired way.
Although the foregoing invention has been described in some detail for the purposes of clarity, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.
Claims
1. A well-tap structure, comprising:
- a well of a first doping type;
- a diffusion region of the first doping type formed in the well; and
- a gate-like structure formed directly above a portion of the well, wherein the diffusion region is formed directly adjacent to the portion of the well.
2. The well-tap structure as defined in claim 1, further comprising:
- an additional diffusion region of the first doping type formed directly adjacent to the the portion of the well, wherein the portion of the well is interposed between the diffusion region and the additional diffusion region.
3. The well-tap structure as defined in claim 1, wherein the diffusion region has a doping concentration, and wherein the well has a doping concentration that is less than the doping concentration of the diffusion region.
4. The well-tap structure as defined in claim 1, wherein the well comprises a p-well.
5. The well-tap structure as defined in claim 4, wherein the diffusion region is coupled to a ground power supply voltage terminal.
6. The well-tap structure as defined in claim 5, wherein the gate-like structure is coupled to a positive power supply voltage terminal.
7. The well-tap structure as defined in claim 1, wherein the well comprises an n-well.
8. The well-tap structure as defined in claim 7, wherein the diffusion region is coupled to a positive power supply voltage terminal.
9. The well-tap structure as defined in claim 8, wherein the gate-like structure is coupled to a ground power supply voltage terminal.
10. An integrated circuit, comprising:
- an array of active structures;
- an array of dummy structures that surrounds the array of active structures; and
- a plurality of well-tap structures interposed between the array of active structures and the array of dummy structures, wherein each well-tap structure in the plurality of well-tap structures includes an associated gate-like conductor.
11. The integrated circuit as defined in claim 10, wherein the active structure is a functional transistor structure, and wherein the dummy structure is a non-functional transistor structure.
12. The integrated circuit as defined in claim 10, wherein the active structures within the array of active structures comprise matching transistor structures.
13. The integrated circuit as defined in claim 10, wherein the associated gate-like structure for each of the well-tap structures is formed adjacent to a well-tap contact of the well-tap structure.
14. The integrated circuit as defined in claim 13, wherein a distance between the plurality of well-tap structures and a center of the array of active structures is less than 30 microns.
15. The integrated circuit as defined in claim 13, wherein the array of dummy structures surrounds the array of active structures to at least 50 microns from the center of the array of active structures.
16. An integrated circuit device, comprising:
- an array of transistor structures, wherein a column in the array of transistor structures comprises: at least one active transistor; at least one dummy transistor; and a well-tap structure interposed between the active transistor and the dummy transistor in the column.
17. The integrated circuit device as defined in claim 16, wherein diffusion regions for the active transistor, the dummy transistor, and the well-tap structure have same width and length.
18. The integrated circuit device as defined in claim 16, wherein the well-tap structure has an associated gate-like structure formed over a semiconductor substrate.
19. The integrated circuit device as defined in claim 18, wherein the gate-like structure forms part of a decoupling capacitor.
20. The integrated circuit as defined in claim 10, wherein each well-tap structure in the plurality of well-tap structures further includes a diffusion region of a given doping type that is formed in a well of the given doping type.
| 5679967 | October 21, 1997 | Janai |
| 5990502 | November 23, 1999 | Park |
| 6756612 | June 29, 2004 | Nemati |
| 6831346 | December 14, 2004 | Li |
| 7250660 | July 31, 2007 | Huang |
| 7404154 | July 22, 2008 | Venkatraman |
| 7468617 | December 23, 2008 | Sengupta |
| 7746696 | June 29, 2010 | Paak |
| 7808047 | October 5, 2010 | Gallerano |
| 7932563 | April 26, 2011 | Ho et al. |
| 8217464 | July 10, 2012 | Do et al. |
| 8314635 | November 20, 2012 | Law et al. |
| 8472227 | June 25, 2013 | Liaw |
| 8836408 | September 16, 2014 | den Besten |
| 8952424 | February 10, 2015 | Herberholz |
| 20030107069 | June 12, 2003 | Takao |
| 20050044522 | February 24, 2005 | Maeda |
| 20060033163 | February 16, 2006 | Chen |
| 20070168899 | July 19, 2007 | Frenkil |
| 20070253257 | November 1, 2007 | Wang |
| 20090026573 | January 29, 2009 | Oh |
| 20090085068 | April 2, 2009 | Furukawa |
| 20090091973 | April 9, 2009 | Sarin |
| 20110171794 | July 14, 2011 | Seo |
| 20110233624 | September 29, 2011 | Fujishiro |
| 20110233687 | September 29, 2011 | Shima |
| 20110305084 | December 15, 2011 | Park |
| 20110317467 | December 29, 2011 | Nagayama |
| 20130089978 | April 11, 2013 | Noel |
| 20140346603 | November 27, 2014 | Toh et al. |
| 20140367791 | December 18, 2014 | Katakami |
| 20150187431 | July 2, 2015 | Chung |
| 20150228649 | August 13, 2015 | Singh |
| 20150294732 | October 15, 2015 | Chung |
| 20160026207 | January 28, 2016 | Boling |
| 20160049190 | February 18, 2016 | Han |
| 20160254445 | September 1, 2016 | Tahmasebi |
| 20160276407 | September 22, 2016 | Naik |
| 20160276580 | September 22, 2016 | Tahmasebi |
| 20160284720 | September 29, 2016 | Ema |
| 20160284763 | September 29, 2016 | Tahmasebi |
Type: Grant
Filed: May 21, 2015
Date of Patent: Apr 18, 2017
Assignee: Altera Corporation (San Jose, CA)
Inventors: Yue Teng Tang (Bayan Lepas), Albert Victor Kordesch (Georgetown)
Primary Examiner: Ngan Ngo
Application Number: 14/719,078
International Classification: H01L 27/00 (20060101); H01L 29/78 (20060101); H01L 27/06 (20060101); H01L 29/10 (20060101); H01L 27/02 (20060101); H01L 27/118 (20060101); H01L 29/66 (20060101); H01L 21/8238 (20060101); H01L 29/06 (20060101);
