Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts

Abstract

A method for maintaining optimum biasing voltage and standby current levels in a dynamic random access memory array, in which row-to-column shorts have been repaired by redirecting the addresses of shorted rows and columns to spare rows and columns. The method partly consists of placing a current limiting device in series with the bias voltage generator output and the nodes between the equilibration transistors of small groups of digit line pairs. The current limiting devices may be either long-L transistors that are in an always-on state, or they may be merely resistive elements, such as strips of lightly-doped polysilicon. The invention effectively isolates the effect of row-to-column shorts in a portion of a DRAM array from the remainder of the array. All digit line pairs tied to a single current limiting device are replaced as a unit if any one or more of the digit lines among the tied pairs is shorted to a word line.The method further consists of holding the common node of each P-type sense amplifiers at no more than a threshold voltage above ground potential during digit line equilibration, rather than at half of power supply voltage, in order to eliminate an unwanted current path from an off-chip power supply, through sundry intervening circuitry, to the common node of a P-type sense amplifier, through the transistors of the P-type sense amplifier, to a bitline which is shorted to one of the rowlines, which are normally held at ground potential during the same period.

Claims

2. The method of claim 1, which further comprises the step of holding the common node of each P-type sense amplifier at ground potential during digit line equilibration.

3. The method of claim 1, wherein said current limiting device is a long channel length, narrow channel width transistor that is in an always-on state.

4. The method of claim 2, wherein said current limiting device is a long channel length, narrow channel width transistor that is in an always-on state.

5. The method of claim 2, wherein sad current limiting device is a resistor.

6. The method of claim 2, wherein aid current limiting device is a resistor.

7. The method of claim 1, which further comprises the step of holding the common node of each P-type sense amplifier at a potential no greater than a threshold voltage above ground potential during digit line equilibration.

8. A method for maintaining optimum bias voltage and standby current levels in a dynamic random access memory array, said memory array having a plurality of row lines which intersect a plurality of column lines, the intersection of a single row line and a single column line providing a storage location for a single bit of data, said column lines being organized in pairs, each pair being coupled to both a single N-type sense amplifier comprising a pair of cross coupled N-channel transistors and a single P-type sense amplifier comprising a pair of cross-coupled P-channel transistors having a common node, said array also having at least one generator for producing a bias voltage from a supply voltage provided form an off-chip source, said bias voltage being applied to each digit line pair during digit line equilibration, said array also being repairable with respect to row line to column line shorts by redirecting the addresses of shorted rows and columns to spare rows and columns said method comprising the steps of:

(a) organizing all digit line pairs within the array into a multiplicity of digit line pair sets, each set having its own biasing voltage supply path, current through each supply path being limited by at least one current-limiting device so as to protect the generator from deleterious voltage drops caused by a row line to column line short within any set; and

(b) holding the common node of each P-type sense amplifier at a potential no greater than a threshold voltage above ground potential during digit line equilibration, in order to eliminate an unwanted current path from the off-chip source, through the transistors of a P-channel sense amplifier, to a bit-line which is shorted to one of the rowlines that are being held at ground potential during digit line equilibration.

9. The method of claim 8, wherein said current limiting device is a long channel length, narrow channel width transistor that is in an always-on state.

10. The method of claim 8, wherein said current limiting device is a resistor.

11. A method for maintaining optimum bias voltage and standby current levels in a dynamic random access memory array, said memory array having a plurality of row lines which intersect a plurality of column lines, the intersection of a single row line and a single column line providing a storage location for a single bit of data, said column lines being organized in pairs, each pair being coupled to both a single N-type sense amplifier comprising a pair of cross-coupled N-channel transistors and a single P-type sense amplifier comprising a pair of cross-coupled P-channel transistors having a common node, said array also having at least one generator for producing a bias voltage that is applied to each digit line pair during digit line equilibration, said array also being repairable with respect to row line to column line shorts by redirecting the addresses of shorted rows and columns to spare rows and columns, said method comprising the steps of:

(a) organizing all digit line pairs within the array into a multiplicity of digit line pair sets, each set having its own biasing voltage supply path, current through each supply path being limited by at least one current-limiting device so as to protect the generator from deleterious voltage drops caused by a row line to column line short within any set; and

(b) holding the common node of each P-type sense amplifier at a potential no greater than a threshold voltage above ground potential during digit line equilibration.

12. The method of claim 11, wherein said current limiting device is a long channel length, narrow channel width transistors that is in an always-on state.

13. The method of claim 11, wherein said current limiting device is a resistor..Iadd.

14. A method for preventing excessive standby current levels in a dynamic random access memory, said memory having a plurality of row lines which intersect a plurality of column lines which are functionally organized as column line pairs, the intersection of a row line and a column line providing a storage location for a single bit of data, each row line and each column line pair having a designated address, each column line pair being coupled to both an N-type sense amplifier comprising a pair of cross-coupled N-channel transistors and a P-type sense amplifier comprising a pair of cross-coupled P-channel transistors, said memory having at least one generator for producing a bias voltage which is applied to each digit line pair during digit line equilibration, said memory also being repairable with respect to row line to column line shorts by redirecting the addresses of shorted row lines and shorted column lines to spare row lines and spare column lines, respectively, said method comprising the steps of:

(a) functionally organizing all column line pairs within the memory into a multiplicity of column line pair sets, each set comprising at least one column line pair; and

(b) providing a separate biasing voltage supply path for each digit line pair set, each path having at least one current-limiting device therein to limit current flow therethrough..Iaddend..Iadd.15. A dynamic random access memory device comprising:

(a) an array of memory cells;

(b) an access device for each memory cell, each access device having a control gate;

(c) a plurality of digit lines, said digit lines being functionally organized into digit line pairs, and said digit line pairs being functionally organized into digit line pair sets, each set comprising at least one digit line pair;

(d) a plurality of word lines which intersect the digit line pairs, each of said word lines being coupled to multiple control gates, each control gate being coupled to a single word line;

(e) at least one biasing voltage source;

(e) a biasing voltage supply path for each digit line pair set, said biasing voltage supply path coupling each digit line within its respective set to the biasing voltage source during periods of digit line equilibration; and

(f) at least one current-limiting device within each biasing voltage supply

path..Iaddend..Iadd.16. The array of claim 15, wherein the each access device is an insulated-gate field-effect transistor and the array further comprises:

an N-channel sense amplifier and a P-channel sense amplifier coupled to each digit line pair, each of said sense amplifiers being constructed from a pair of series-coupled field-effect transistors, with the transistors of each transistor pair sharing a common node..Iaddend..Iadd.17. The array of claim 16, wherein the common node associated with the transistor pair having a channel type opposite that of the cell access devices is maintained at less than a threshold voltage from the potential at which the word lines are maintained during digit line equilibration.

.Iaddend..Iadd.18. The array of claim 15, wherein said current-limiting device is a resistor..Iaddend..Iadd.19. The array of claim 15, wherein said current-limiting device is a transistor..Iaddend..Iadd.20. The array of claim 19, wherein said transistor is in an always-on state..Iaddend..Iadd.21. The array of claim 19, wherein said transistor is a field effect transistor having a channel, the length of which is more than thrice the width thereof..Iaddend..Iadd.22. A memory device comprising:

(a) a plurality of digit lines, said digit lines being functionally organized into digit line sets, each set comprising multiple digit lines;

(b) at least one biasing voltage source;

(c) a separate biasing voltage supply path for each digit line set which selectively couples said biasing voltage source to the digit lines of its respective set; and

(d) at least one current-limiting device within each biasing voltage supply

path..Iaddend..Iadd.23. A dynamic random access memory comprising:

(a) a plurality of memory cells, each memory cell having a field-effect transistor as an access device, each of said access devices having a control gate;

(b) a plurality of digit line pairs, said digit line pairs being functionally organized into digit line pair sets, each set comprising at least one digit line pair;

(c) a plurality of word lines which intersect said digit line pairs, the intersection of each word line and each digit line pair corresponding to a single memory cell location within the memory, each word line being coupled to multiple control gates, each control rate being coupled to a single word line;

(d) an N-channel sense amplifier and a P-channel sense amplifier coupled to each digit line pair, each of said sense amplifiers being constructed from a pair of series-coupled field-effect transistors, with each pair of transistors sharing a common node;

(e) at least biasing voltage source;

(f) a biasing voltage supply path for each digit line set, said path coupling said biasing voltage source to the digit lines of its respective set during periods of digit line equilibration; and

(g) at least one current-limiting device within each biasing voltage supply

path..Iaddend..Iadd.24. The memory array of claim 23, wherein the common node associated with the transistor pair having a channel type opposite that of the cell access transistors is maintained at less than a threshold voltage from the potential at which the word lines are maintained during

digit line equilibration..Iaddend..Iadd.25. A memory device comprising:

a pair of digit lines;

a pair of equilibration devices coupled together in series to said digit lines, said equilibration devices coupled together at a common node and responsive to an equilibration signal to couple the common node to said digit lines;

a bias voltage generator; and

a current limiting device coupled in series to the common node and to an

output of said bias voltage generator..Iaddend..Iadd.26. A memory device, comprising:

a first digit line;

a second digit line;

an equilibration device coupled to said first digit line and to said second digit line responsive to an equilibration signal to couple said first digit line to said second digit line;

a bias voltage generator;

a current limiting device coupled to said bias voltage generator; and

an isolation device coupled in series with said first digit line and said current limiting device..Iaddend..Iadd.27. A device, comprising:

a plurality of digit line pairs;

a current limiting device;

a plurality of equilibration devices, at least one equilibration device coupled between the digit lines of each digit line pair; and

a bias voltage generator coupled to said plurality of equilibration devices through said current limiting device..Iaddend.