Method of manufacturing inversion type IC's and IC module using same
A method of manufacturing inversion ICs includes the steps of connecting a first electrode pad group of a semiconductor chip to a second lead group via wires, connecting a second electrode pad group of the semiconductor chip to a first lead group via wires, sealing the semiconductor chip, the first and second lead groups, and the wires in a resin so that the outer lead portions of the leads are exposed, and bending the outer lead portions of the leads toward the bottom surface of the semiconductor chip. An IC module includes a mounting substrate, a standard IC mounted on the top surface of the mounting substrate, an inversion IC mounted on the bottom surface of the mounting substrate so that the leads providing connections to the same functions in the standard and inversion ICs are at the same point on opposite sides of the mounting substrate, and a plurality of connecting members on the mounting substrate, electrically connecting the opposed leads of the standard IC and the leads of the inversion IC together.
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Claims
1. The method of making pairs of packaged semiconductor chips having inverted lead relationships for direct mounting and parallel electrical connection of the pairs of packaged semiconductor chips with the packaged semiconductor chips opposed to each other, the method comprising:
- preparing identical first and second semiconductor chips, each semiconductor chip including opposed top and bottom surfaces.Iadd., opposed first and second edges,.Iaddend.and first and second rows of electrode pads disposed on the top surface.Iadd.proximate the first and second edges, respectively.Iaddend.;
- mounting the first semiconductor chip on a die pad of a first lead frame, the first lead frame including first and second rows of peripherally disposed leads, the first row of leads being disposed proximate.Iadd.the first edge and.Iaddend.the first row of electrode pads of the first semiconductor chip and the second row of leads being disposed proximate.Iadd.the second edge and.Iaddend.the second row of electrode pads of the first semiconductor chip;
- connecting the electrode pads of the first semiconductor chip in the first row to corresponding leads in the first row of leads of the first lead frame with wires and connecting the electrode pads of the first semiconductor chip in the second row to corresponding leads in the second row of leads of the first lead frame with wires;
- encapsulating the first semiconductor chip, the die pad of the first lead frame, the wires, and parts of the leads of the first lead frame in a resin with part of the leads of the first lead frame extending from the resin; and
- bending the leads protruding from the resin encapsulating the first semiconductor chip toward the bottom surface of the first semiconductor chip;
- mounting the second semiconductor chip on a die pad of a second lead frame, the second lead frame including first and second rows of peripherally disposed leads,.Iadd.the first row of leads being disposed proximate the first edge and the second leads being disposed proximate the second edge,.Iaddend.the leads of the second lead frame extending across at least part of the die pad of the second lead frame and spaced from the top surface of the second semiconductor chip, the first row of leads including ends proximate the second row of electrode pads of the second semiconductor chip, and the second row of leads including ends proximate the first row of electrode pads of the second semiconductor chip;
- connecting the electrode pads of the second semiconductor chip in the first row to corresponding leads in the second row of leads of the second lead frame with wires and connecting the electrode pads of the second semiconductor chip in the second row to corresponding leads in the first row of leads of the second lead frame with wires;
- encapsulating the second semiconductor chip, the die pad of the second lead frame, the wires, and parts of the leads of the second lead frame in a resin with part of the leads of the second lead frame extending from the resin; and
- bending the leads protruding from the resin encapsulating the second semiconductor chip toward the bottom surface of the second semiconductor chip.Iadd.whereby the encapsulated first and second semiconductor chips have inverted lead relationships.Iaddend..
4. The packaged semiconductor chip module of claim 3 wherein each of the non-inverted packaged semiconductor chip and the inverted packaged semiconductor chip includes a resin package encapsulating the first and second semiconductor chips, the wires, and parts of the first and second rows of leads so that outer portions of the leads protrude from the respective packages and each of the leads in the inverted packaged semiconductor chip crosses part of and is spaced from the top surface of the second semiconductor chip.
5. The packaged semiconductor chip module of claim 4 wherein the inverted and non-inverted packaged semiconductor chips are substantially rectangular and the outer lead portions extend from opposite sides of each of the inverted and non-inverted semiconductor chip packages.
6. The packaged semiconductor chip module of claim 4 wherein the inverted and non-inverted packaged semiconductor chips are substantially rectangular and the outer lead portions extend from four sides of each of the inverted and non-inverted semiconductor chip packages.
8. The packaged semiconductor chip module of claim 7 wherein each of the non-inverted packaged semiconductor chip and the inverted packaged semiconductor chip includes a resin package encapsulating the first and second semiconductor chips, the wires, and the first and second rows of leads so that outer portions of the leads protrude from the respective packages and each of the leads in the inverted packaged semiconductor chip crosses part of and is spaced from the top surface of the second semiconductor chip.
9. The packaged semiconductor chip module of claim 8 wherein the inverted and non-inverted packaged semiconductor chips are substantially rectangular and the outer lead portions extend from opposite sides of each of the inverted and non-inverted semiconductor chip packages.
10. The packaged semiconductor chip module of claim 8 wherein the inverted and non-inverted packaged semiconductor chips are substantially rectangular and the outer lead portions extend from four sides of each of the inverted and non-inverted semiconductor chip packages.
12. The packaged semiconductor chip module of claim 11 wherein each of the non-inverted packaged semiconductor chip and the inverted packaged semiconductor chip includes a resin package encapsulating the first and second semiconductor chips, the wires, and parts of the first and second rows of leads so that outer portions of the leads protrude from the respective packages and each of the leads in the inverted packaged semiconductor chip crosses part of and is spaced from the top surface of the second semiconductor chip.
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Type: Grant
Filed: Jun 23, 1995
Date of Patent: Feb 2, 1999
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo)
Inventors: Kazunari Michii (Itami), Hiroshi Seki (Itami)
Primary Examiner: Donald Sparks
Law Firm: Leydig, Voit & Mayer
Application Number: 8/494,065
International Classification: H05K 502; H01R 4316; H01L 23495; H01L 2160;