Fabrication of an integrated circuit package
A QFN integrated circuit is mounted on a leadframe having multiple lead lands and resin material encapsulates the integrated circuit leaving the lead lands exposed. Subsequently a sawing operation divides the lead lands into multiple leads, and the leadframe and resin material are partitioned to form packages. The pitch of the resultant leads is not limited by the pitch of the lead lands of the leadframe, so the leadframe can be of the relatively cheap generic leadframe variety, in which the pitch of the lead lands is higher than the desired pitch of the leads of the completed package. The sawing operation may further include reshaping the diepad area of the leadframe to produce heat sink fins, for improved heat dissipation. The proposed process is suitable both to produce packages including only a single integrated circuit, and also to produce multi-chip modules.
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This application This application is a reissue application of U.S. Pat. No. 7,618,845 B2, entitled “Fabrication of an Integrated Circuit Package,” issued on Nov. 17, 2009, which is a continuation-in-part of co-pending International Application No. PCT/SG2006/000017, filed Feb. 1, 2006, which is incorporated herein by reference.
TECHNICAL FIELDThe present invention relates to a method for fabricating an integrated circuit package, particularly but not exhaustively to a method for fabricating a quad-flat non-leaded (QFN) integrated circuit package, and packages produced by the method.
BACKGROUNDA QFN integrated circuit is a semiconductor device having a generally-rectangular (usually square) upper surface with electrical contacts along its edges. Existing techniques for packaging a QFN integrated circuit to produce a package make use of a leadframe produced by etching. The packaging technique is illustrated below with reference to
As shown in
Subsequently, as shown in
Then, as shown in
As shown in
Note that the process above uses an etched leadframe. This is because conventional stamped leadframes cannot be used to produce leadframes with very tiny lead pitch (e.g., under 0.8 mm), since the leadframe punching tool would be easily broken. However, the use of the etched leadframes with small and/or custom designed lead pitch leads to a number of disadvantages.
Firstly, as the lead pitch becomes smaller, the cost of producing the etched leadframes is rising. Practically speaking, it is very difficult to produce an etched leadframe with a pitch less than 0.5 mm, and certainly very expensive to do so.
Secondly, since etched leadframes are usually pre-designed and etched at a specialist manufacturing location, making any modification of the design is logistically difficult, leading to rigidity in the process.
Thirdly, the presence of the tape 7 causes “lead bouncing,” which causes wire bonding difficulties such as bonded wire stress necks and crack stitches, and therefore marginal bonding reliability concerns.
Fourthly, taping the individual tiny leads 3, 5 causes mold resin bleeding and the issue of mold flashes. This may lead to a solderability failure.
SUMMARY OF THE INVENTIONThe present invention aims to provide new and useful techniques for packaging an integrated circuit, and to provide new and useful packages.
In various embodiments, the present invention proposes that an integrated circuit is mounted on a leadframe having multiple lead lands, and that subsequently a shaping operation is performed on the leadframe to divide at least one of the lead lands into multiple leads.
Note that the pitch of the final leads is not limited by the pitch of the lead lands of the leadframe. This means that the leadframe can be a relatively cheap generic leadframe in which the pitch of the lead lands is higher than the desired pitch of the leads of the completed package.
Furthermore, a single type of generic leadframe may be used to produce packages having a range of lead pitches by varying how the partitioning process is carried out. The designer of the integrated circuit package can choose whatever pitch is most suitable for the application without being limited by the initial configuration of the lead lines.
From another point of view, since the final configuration of the leads is determined by the shaping operation, it does not have to be determined at the time that the leadframe is manufactured. This means gives much increased flexibility to the designer of the integrated circuit package.
Wire bonding may be performed prior to the shaping of the lead lands. The lead lands may be relatively wide (i.e., before they have been partitioned), so that the wire bonding may be performed more effectively, typically producing a low level of lead bouncing.
Furthermore, the process may include taping and molding/encapsulation before the shaping of the lead lands, at a time when the lead lands are larger than the leads of the completed package. The greater size of the lead lands may result in reduced mold resin bleeding and fewer flashes. Thus, the molding process may be more robust.
The sawing operation may optionally include reshaping the leadframe to produce heat sink fins, which may have the advantage of improved heat dissipation.
The proposed process is suitable both to produce packages including only a single integrated circuits (i.e., the QFN integrated circuit), and also packaging including multiple dies, so-called MCM (multi-chip modules).
The leadframe may be a stamped or etched leadframe.
In further aspects, the invention provides a package produced by the method, and the leadframe used in the method. The leadframe typically includes a diepad region and at least one lead land located to a respective side of the diepad region. The lead land is preferably substantially as long in the direction parallel to side of the diepad region as the side of a typical QFN integrated circuit. For example, the lead land may be at least 2 mm in length in that direction, or at least 4 mm in length in that direction. It is typically at least as long, and more typically at least twice as long, as its extension in the direction in which it is spaced from the diepad.
In a specific expression of the invention there is provided a method of packaging a QFN integrated circuit. The QFN integrated circuit is located on a diepad of a leadframe including one or more lead lands extending in a direction parallel to an adjacent side of the diepad. Wire bonds are formed between electrical contacts of the integrated circuit and the lead lands of the leadframe. The integrated circuit and the leadframe are encapsulated in a resin material, leaving a portion of the lead lands exposed. One or more of the lead lands are shaped in a direction perpendicular to an adjacent side of the diepad to divide the one or more lead lands into multiple respective leads.
Non-limiting embodiments of the invention will now be described for the sake of example only with reference to the following figures, in which:
In a first embodiment of the invention, a method 200 packaging is as shown in
In step 202 the leadframe and diepad are positioned on a tape. In step 204 a QFN die is placed onto the diepad. In step 206 wire bonds are formed between the die contents and the lead lands. In step 208 the die and leadframe are encapsulated. In step 210 the tape is removed. In step 212 the lead tape residues are removed and silver plating is performed. In step 214 strip lamination is performed to form a foil. In step 216 the lead lands and diepad are sawed to form the leads and heat dissipation fins. In step 218 unit singulation is performed. In step 220 the singulated unit is tested. In step 222 the singulated unit is lifted and stored for later use.
The method 200 in
The die bonding step 204 may be implemented by placing a QFN die 29 onto diepad 21, as shown in
Subsequently, the wire bonding step 206 may be implemented as shown in
The encapsulation step 208 may be implemented as shown in
The tape removal step 210 may be implemented as shown in
The residue removal step 212 may be implemented by the lead tape residues being removed by cleaning, and Ag plating. Note that the lead lands 23, 25 are exposed on the lower surface of the resin material 28.
The strip lamination step 214 may be implemented, as shown in
The sawing step 216 may be implemented by one or more locations on the exposed surface of the leadframe being shaped by a sawing process using a rotary blade 22, which advances in the direction of the arrow, as shown in
The singulation step 218 may be implemented by unit singulation being performed by cutting the resin body 28 to form package units 34.
The testing step 220 subsequently, as shown in
The lifting step 222 may be implemented as shown in
The sawing step 216 shown in
The sawing is perpendicular to the side 37 of the diepad adjacent the lead land 25. The cuts in the lead lands 23, 25, therefore, transversely divide each of the lead lands 23, 25 into five separate electrically isolated leads 41, 43. Note that the pitch of (i.e., spacing between) the five leads produced from each lead land is less than the original pitch of the lead lands 23, 25, so that latter pitch does not need to be particularly low: a pitch of say up to 0.5 mm would be suitable. Such a leadframe can be produced at low cost. Due to the sawing operation, the pitch of the resultant leads 41, 43 can be selected to be any desired value. The leads 41, 43 are shown in
The cuts formed by sawing the lower surface of the diepad 21 form a number of grooves (or gaps), and thus shape the lower surface of the diepad 21 into heat sink fins 44, best seen in
While in the first embodiment there is only a single QFN integrated circuit in the completed package 34, in a second embodiment produced by a process shown in
As in the first embodiment, there is an initial step in which a leadframe having a diepad 41 and lead lands 43, 45 is positioned on a tape 47, as shown in
Subsequently, as shown in
Then a sawing process is performed, as shown in
Note that, as in the first embodiment, the lead pitch of the leadframe prior to the sawing does not need to be particularly low: a pitch of say up to 0.5 mm would be suitable. Such a leadframe can be produced at low cost. Due to the sawing operation, the leads are divided, to produce reshaped leads with a small pitch of whatever value is desired in this application. The lower surface of the diepad 41 is shaped to include a number of grooves (or even gaps) which form fins to function as a heat sink for dissipating heat generated by the QFN integrated circuit.
Although the fins of the embodiments of
The leadframe used may be of a type as appropriate for a given application. For example, a stamped leadframe may be produced by pressing a sheet of conductive material to remove portions of the sheet. A further example is using an etched leadframe with a single etched lead land instead of individual leads with small and/or custom designed lead pitch. Further examples will be apparent to the skilled reader.
Many variations are possible within the scope of the claims, as will be clear to a skilled reader.
Claims
1. A method of packaging an integrated circuit, the method comprising:
- locating the integrated circuit on a diepad of a leadframe that includes a lead land comprising an adjacent portion that extends in a direction parallel to an adjacent side of the diepad;
- forming wire bonds between electrical contacts of the integrated circuit and the lead land of the leadframe;
- encapsulating the integrated circuit and the leadframe in a resin material, leaving a portion of the lead land exposed; and
- after encapsulating, shaping the adjacent portion of the lead land only in a direction substantially perpendicular to the adjacent side of the diepad to divide the lead land into multiple leads bonded to the contacts of the integrated circuit, the shaping performed on a portion of the lead land directly adjacent to the adjacent side of the diepad.
2. The method according to claim 1, wherein the shaping is performed by sawing.
3. The method according to claim 1, wherein the shaping further includes shaping at least part of an exposed surface of the diepad to form heat dissipation fins.
4. The method according to claim 1, wherein, after the shaping, singulation is performed in which the resin material and the leadframe are partitioned to form individual integrated circuit packages.
5. The method according to claim 4, wherein, following the singulation, at least one of the individual integrated circuit packages comprise a plurality of integrated circuits.
6. The method according to claim 1, wherein the leadframe comprises a stamped leadframe.
7. The method according to claim 1, wherein the leadframe comprises an etched leadframe.
8. An integrated circuit package produced by a method comprising:
- locating the integrated circuit on a diepad of a leadframe that includes a lead land comprising an adjacent portion that extends in a direction parallel to an adjacent side of the diepad;
- forming wire bonds between electrical contacts of the integrated circuit and the lead land of the leadframe;
- encapsulating the integrated circuit and the leadframe in a resin material, leaving a portion of the lead land exposed; and
- after encapsulating, shaping the adjacent portion of the lead land only in a direction substantially perpendicular to the adjacent side of the diepad to divide the lead land into multiple leads bonded to the contacts of the integrated circuit, the shaping performed on a portion of the lead land directly adjacent to the adjacent side of the diepad.
9. A leadframe for use in a method comprising:
- locating an integrated circuit on a diepad of the leadframe that includes a lead land comprising an adjacent portion that extends in a direction parallel to an adjacent side of the diepad;
- forming wire bonds between electrical contacts of the integrated circuit and the lead land of the leadframe;
- encapsulating the integrated circuit and the leadframe in a resin material, leaving a portion of the lead land exposed; and
- after encapsulating, shaping the adjacent portion of the lead land only in a direction substantially perpendicular to the adjacent side of the diepad to divide the lead land into multiple leads bonded to the contacts of the integrated circuit, wherein the leadframe includes a diepad region and one or more lead lands extending along a respective side of the diepad region, and the shaping is performed on a portion of the lead land directly adjacent to the adjacent side of the diepad.
10. The method according to claim 1, wherein the lead land comprises a plurality of lead lands.
11. The method of claim 1, wherein the integrated circuit comprises a quad-flat non-leaded (QFN) integrated circuit.
12. The method of claim 1, wherein the adjacent portion of the lead land comprises a length in the direction parallel to the adjacent side of the diepad at least twice as long as a width in the direction perpendicular to the adjacent side of the diepad.
13. The integrated circuit package of claim 8, wherein the integrated circuit packages comprises a quad-flat non-leaded (QFN) integrated circuit package.
14. A method of packaging an integrated circuit, the method comprising:
- placing the integrated circuit on a diepad of a leadframe comprising a lead land comprising an adjacent portion that extends in a direction parallel to an adjacent side of the diepad;
- forming wire bonds between electrical contacts of the integrated circuit and the lead land of the leadframe;
- encapsulating the integrated circuit and the leadframe in a resin material, leaving a portion of the lead land exposed; and
- after encapsulating, sawing the adjacent portion of the lead land only in a direction substantially perpendicular to the adjacent side of the diepad to divide the lead land into multiple leads bonded to the contacts of the integrated circuit, the sawing performed on a portion of the lead land directly adjacent to the adjacent side of the diepad.
15. A method of packaging an integrated circuit, the method comprising:
- locating the integrated circuit on a diepad of a leadframe that includes a lead land comprising an adjacent portion that extends in a direction parallel to an adjacent side of the diepad, wherein the die pad is separate from the lead land;
- forming wire bonds between electrical contacts of the integrated circuit and the lead land of the leadframe;
- encapsulating the integrated circuit and the leadframe in a resin material, leaving a portion of the lead land exposed; and
- after encapsulating, shaping the adjacent portion of the lead land only in a direction substantially perpendicular to the adjacent side of the diepad to divide the lead land into multiple leads bonded to the contacts of the integrated circuit, the shaping performed on a portion of the lead land directly adjacent to the adjacent side of the diepad.
16. The method according to claim 15, wherein shaping is performed by sawing.
17. The method according to claim 15, wherein, after the shaping, singulation is performed in which the resin material and the leadframe are partitioned to form individual integrated circuit packages.
18. A method of packaging an integrated circuit, the method comprising:
- placing the integrated circuit on a diepad of a leadframe comprising a lead land comprising an adjacent portion that extends in a direction parallel to an adjacent side of the diepad;
- forming wire bonds between electrical contacts of the integrated circuit and the lead land of the leadframe;
- encapsulating the integrated circuit and the leadframe in a resin material, leaving a portion of the lead land exposed; and
- after encapsulating, making cuts in the adjacent portion of the lead land only in a direction substantially perpendicular to the adjacent side of the diepad, wherein multiple respective leads are formed between the cuts, the making cuts performed on a portion of the lead land directly adjacent to the adjacent side of the diepad.
19. The method of claim 18, wherein making cuts in the lead land comprises sawing the lead land.
20. A method of packaging an integrated circuit, the method comprising:
- locating the integrated circuit on a diepad of a leadframe that includes a lead land comprising an adjacent portion that extends in a direction parallel to an adjacent side of the diepad;
- forming wire bonds between electrical contacts of the integrated circuit and the lead land of the leadframe;
- encapsulating the integrated circuit and the leadframe, leaving a portion of the lead land exposed; and
- after encapsulating, shaping the adjacent portion of the lead land only in a direction substantially perpendicular to the adjacent side of the diepad to divide the lead land into multiple leads bonded to the contacts of the integrated circuit, the shaping performed on a portion of the lead land directly adjacent to the adjacent side of the diepad.
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Type: Grant
Filed: Nov 17, 2011
Date of Patent: Nov 20, 2012
Assignee: Infineon Technologies AG (Munich)
Inventor: Chee Chian Lim (Alor Gajah Melaka)
Primary Examiner: Fernando L Toledo
Assistant Examiner: Karen Kusumakar
Attorney: Slater & Matsil, L.L.P.
Application Number: 13/299,033
International Classification: H01L 21/00 (20060101); H01L 23/28 (20060101); H01L 23/48 (20060101); H01L 23/495 (20060101);