Abstract: In a method of estimating a leakage current in semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of the cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function is generated by arithmetically operating the virtual cell leakage characteristic functions of each cell in the segment. Then, a full chip leakage characteristic function is generated by statistically operating the segment leakage characteristic functions of each segment in the chip. Accordingly, the computational loads of Wilkinson's method for generating the full chip leakage characteristic function may be remarkably reduced.

Abstract: Embodiments of methods and apparatus for optimization of verification of a chip design are disclosed. In various embodiments, a method for reducing a number of points to be verified during a verification process is disclosed, the method comprising selecting a first and a second verification point of a model of an integrated circuit design, determining whether the first and second verification points are isomorphic, and outputting the result of the determining to enable the first and second verification points being verified by verifying only a selected one of the first and second verification points in case the first and the second verification points are isomorphic. Additional variants and embodiments may also be disclosed and claimed.

Abstract: Embodiments that make DFM alterations to cells of 1×N building blocks via a closed-loop 1×N compiler are disclosed. Some embodiments comprise using a 1×N compiler to detect a relationship between two adjacent cells of a 1×N building block. Based on the relationship, the embodiments select a DFM alteration and apply the alteration to a physical design representation. The embodiments may apply various types of DFM alterations depending on the relationship, such as adding polysilicon, adding metal to create redundant connections, and merging diffusion areas to increase capacitance on supply nodes. Further embodiments comprise an apparatus having a cell examiner to examine two adjacent cells of a 1×N building block and determine a relationship of the two cells. The apparatus also comprises a DFM selector to select a DFM alteration based on the relationship and a DFM applicator to apply the selected DFM alteration to one of the cells.

Abstract: Methods and apparatuses to optimize integrated circuits by identifying functional modules in the circuit having similar functionality that can share circuit resources and producing a modified description of the circuit where the similar functional modules are folded onto common circuit resources and time-multiplexed using an original system clock or a fast clock.

Abstract: A verification assisting apparatus for assisting a matching check between a specification and implementation of an object includes: an obtaining unit that obtains a specification description including elements executed to realize functions of the object and restricting conditions of the elements to realize the functions, and an implementation description concerning the functions; a creating unit that creates a graph structure including, as nodes, the elements and the restricting conditions, based on the implementation description; a first correlating unit that correlates nodes in the graph structure with the implementation description; a second correlating unit that correlates a node in the graph structure with the specification description, by detecting the node in the structure using a description concerning the element or the restricting condition in the specification description; and an outputting unit that outputs the correlation results.

Abstract: A modeling technique is provided. The modeling technique includes inputting tool parameters into a model and inputting basic model parameters into the model. The technique further includes generating a simulated, corrected reticle design using the tool parameters and the basic model parameters. An image of test patterns is compared against the simulated, corrected reticle design. A determination is made as to whether ?1<?-1, wherein ?1 represents model vs. exposure difference and ?-1 represents predetermined criteria. The technique further includes completing the model when ?1<?-1.

Abstract: A logic verification apparatus for verifying a logic circuit includes a line recognition unit that recognizes signal lines in the circuit based on design information regarding the circuit as a starting point; a decoder recognition unit that recognizes an area including an AND gate that outputs a certain logical value and an inverter as a decoder circuit area based on the design information, and determines a logical value of an input signal inputted to the recognized decoder circuit area when a logical value of the starting point has a specific logical value; and a determination unit that determines whether a logical configuration of the recognized decoder circuit area is correct based on the number of input signals and a combination of logical values of input signals between the recognized decoder circuit areas.

Abstract: Mechanisms are provided for performing intrusion searching of a hierarchical integrated circuit design. These mechanisms may receive the hierarchical integrated circuit design and perform a parallel intrusion search operation, that utilizes a substituting scan line, on the hierarchical integrated circuit design to identify intrusions of geometric objects in the hierarchical integrated circuit design. The mechanisms may further record intrusions of geometric objects in the hierarchical integrated circuit design identified by the parallel intrusion search operation. The parallel intrusion search operation may utilize a plurality of separate intrusion searches executed by the data processing system in parallel on the hierarchical integrated circuit design.

Abstract: A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer.

Abstract: This invention discloses a method for automatically generating an integrated circuit (IC) layout, the method comprises determining a first cell height, creating a plurality of standard cells all having the first cell height, and generating the IC layout from the plurality of standard cells by placing and routing thereof.

Abstract: A device includes a processor and a computer-readable medium including computer-readable instructions. Upon execution by the processor, the computer-readable instructions cause the device to receive a first request from a second device, where the first request is a layout request that includes an identification of a space. The computer-readable instructions also cause the device to provide a second request to a third device, where the second request includes the identification of the space. The computer-readable instructions also cause the device to receive one or more dimension corresponding to the space, and to provide the one or more dimension to the third device. The computer-readable instructions further cause the device to receive a generated layout from the third device, and to provide the generated layout to the second device.

Abstract: Embodiments that create parent-child relationships for reuse of 1×N building blocks in a closed-loop 1×N system are disclosed. Some methods comprise generating a representation of an IC design, inserting a first 1×N building block into the representation, and creating an association between the first 1×N building block and a second 1×N building block. The association enables the first 1×N building block to inherit alterations of attributes of the second 1×N building block and enables unique alterations of attributes of the first 1×N building block which differ from the second 1×N building block. Further embodiments comprise an apparatus having an equivalency determiner to determine a logical equivalence between a two 1×N building blocks, an attribute creator that creates a set of attributes and enables one of the 1×N building blocks to inherit parent attributes and comprise child attributes.

Abstract: Embodiments that reassemble hierarchical representations in a closed-loop 1×N system are disclosed. Some embodiments comprise creating a flat netlist from a hierarchical representation of a 1×N building block, creating attributes for the flat netlist, and altering one or more elements of the flat netlist, such as by an operation of a logic design tool, a synthesis tool, a physical design tool, or a timing analysis tool. The embodiments further comprise generating a second hierarchical representation of the 1×N building block that reflects the altered element. Further embodiments comprise an apparatus having a 1×N compiler and a reassembler. The 1×N compiler may create attributes for a flat netlist of elements of a hierarchical representation of a 1×N building block. The reassembler may use the attributes to create a second hierarchical representation of the 1×N building block that reflects alteration of elements to the flat netlist.

Abstract: Embodiments that design integrated circuits using a closed loop 1xN methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1xN building blocks. The embodiments may alter elements of the 1xN building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a viewer and a 1xN compiler. The viewer may generate displays of behavioral representations of 1xN building blocks, with the behavioral representations comprising RTL definitions. The 1xN compiler may create physical design representations of the 1xN building block and create behavioral representations from the physical design representations, wherein the physical design representations have elements altered by one or more tools of a tool suite.

Abstract: Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

Abstract: An automatic wiring method includes calculating a metal area within an integrated circuit, and determining whether the metal area calculated at the calculating is smaller than a minimum metal area as a predetermined threshold value.

Abstract: Partial reconfiguration of programmable logic devices may be achieved in a hardware-controlled manner without relying upon software. Upon installation of a new memory module, partial reconfiguration may enable alteration of a clock frequency without affecting operation of the software. When a new interface is installed, partial reconfiguration will allow a programmable logic device to adapt to either a serial or parallel interface before executing a standard boot-up sequence for the computer system.

Abstract: Embodiments that route 1×N building blocks using higher-level wiring information for a 1×N compiler are disclosed. Some embodiments comprise determining higher-level coordinates for a blockage of a 1×N building block, determining intra-1×N coordinates for a shape of the blockage via the higher-level coordinates, and creating routes of intra-1×N wires of the 1×N building block that avoid the intra-1×N coordinates. Further embodiments comprise an apparatus having a higher-level wiring examiner to examine higher-level wiring of an area near a 1×N building block of a physical design representation. The apparatus may also have a blockage determiner to determine a blockage that affects intra-1×N wiring for the 1×N building block and a coordinate calculator to calculate coordinates of a shape of the blockage, wherein the calculated coordinates may enable a routing tool to avoid the shape when creating intra-1×N wiring for the 1×N building block.

Abstract: A method is disclosed for the integration of an integrated circuit into a standardized software architecture for embedded systems. The method includes a definition of a computer readable standardized data structure which is completed with the properties of the integrated circuit. The completed standardized data structure is then used for the definition of a hardware module which includes the integrated circuit. The hardware module definition thus generated is exported in a form which can be imported by the standardized software architecture for embedded systems for further processing.

Abstract: A method and system for organizing a plurality of files generated by an Electronic Design and Automation (EDA) tool into composite objects is disclosed. The system provides a plurality of rules, which may be configured for various EDA tools. These rules may be configured for any EDA tool by specifying various parameters such as filename patterns, file formats, directory name patterns, and the like. Using these rules which are configured for an EDA tool, the files that form a part of the design objects are identified and packaged in the form of composite objects.

Abstract: Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific elements of the single-channel design (e.g., registers and memories) are replaced with corresponding elements of N-times more capacity for pipelining the signal processing for multiple channels.

Abstract: A method for fracturing or mask data preparation or proximity effect correction of a desired pattern to be formed on a reticle is disclosed in which a plurality of variable shaped beam (VSB) shots are determined which can form the desired pattern. Shots within the plurality of VSB shots are allowed to overlap each other. Dosages of the shots may also be allowed to vary with respect to each other. The union of the plurality of shots may deviate from the desired pattern. The plurality of shots may be determined such that a pattern on the surface calculated from the plurality of shots is within a predetermined tolerance of the desired pattern. In some embodiments, an optimization technique may be used to minimize shot count. In other embodiments, the plurality of shots may be optionally selected from one or more pre-computed VSB shots or groups of VSB shots.

Abstract: A method is described herein for predicting lateral position information about a feature represented in an integrated circuit layout for use with an integrated circuit fabrication process, where the process projects an image onto a resist. The method includes providing a lateral distribution of intensity values of the image at different depths with the resist. Next, the lateral position of an edge point of the feature is predicted in dependence upon a particular resist development time, and further in dependence upon the image intensity values at more than one depth within the resist.

Abstract: A method for optical proximity correction of a design of a pattern on a surface is disclosed with the method comprising the steps of inputting desired patterns for the substrate and inputting a set of characters some of which are complex characters that may be used for forming the patterns on the surface. A method of creating glyphs is also disclosed.

Abstract: A method for fracturing or mask data preparation or proximity effect correction is disclosed which comprises the steps of inputting patterns to be formed on a surface, a subset of the patterns being slightly different variations of each other and selecting a set of characters some of which are complex characters to be used to form the number of patterns, and reducing shot count or total write time by use of a character varying technique. A system for fracturing or mask data preparation or proximity effect correction is also disclosed.

Abstract: Mechanisms that allow frameworks significant flexibility in varying the library of common base classes in a manner that better suits the domain of applications served by the framework. Instead of providing the base class library, the runtime provides a data contract for the data structure of each base class. The frameworks can then define each base class in a custom way so long as the data contract is honored. Thus, for example, the framework may provide custom framework-specific methods and/or properties as is appropriate for the framework. Another framework might define the base classes in a different way.

Abstract: The present invention provides a method, system and computer program product for determining a reuse factor associated with a set of resources available for a project. The method includes identifying the set of resources from a repository. The predetermined saved-effort associated with the set of resources is also determined from the repository. The method further includes identifying one or more resources from the set of resources. The one or more resources are identified by a project leader to be used in the project. Thereafter, the reuse factor is estimated on the basis of the predetermined saved-effort associated with the set of resources and the effort saved by the use of the one or more resources.

Abstract: A compositional or alternate object model is employed over an imperative object model to facilitate inspection and construction of imperative structures in a user-friendly manner. Transformations between compositional and imperative models and vice versa can be specified to provide a bridge between differing computing worlds. Moreover, various architectures and/or design patterns can be employed to effect transformation in different ways.

Abstract: Disclosed herein is a system and a method for creating and facilitating computer-based interactions amongst a group of individuals during a group activity. In an embodiment herein, an activity player is provided for rendering instances of the group activity. A library of activity templates is also provided so that instances of said activity templates may be used to create an activity executable. An activity data file may be created for storing data corresponding to the instances of activity templates used in the activity executable, wherein said activity executable and activity data file are used to create the group activity. Said group activity may be then rendered by the activity player.

Abstract: A system and method for model driven software is disclosed. In one embodiment, the method of handling changes to a software system in a business environment includes capturing customer requirements of the software system in a schema, modeling business-software architecture of the software system in a first level of the schema, modeling design architecture of the software system in a second level of the schema, defining events that connect the first level and second level of the schema, defining links that represent interactions between the user interfaces, defining integration services for each of the events, mapping each element in the first level to a corresponding one of elements in the second level using the events, links and integration services, creating a knowledge repository with a traversable user interface representing the mappings, identifying changes to the software system, and analyzing impact of the changes using the knowledge repository.

Abstract: The present invention refers to a method for structuring a software implementation with a plurality of modules, in particular, Java packages and for checking whether these modules fit a logical model. In a preparation phase the logical model will be defined and consists of two independent dimensions comprising a technical dimension and a business-driven-dimension. Further, allowed dependencies between the elements of the logical model, namely layers and slices, will be defined. In a subsequent implementation phase the modules of the software implementation will be assigned to the logical model. Further, monitoring is done in order to check whether the software implementation comprises any violations of the allowed dependencies. After assigning the modules to the logical model the logical model with the assigned modules will be visualised interactively and integrally and the allowed dependencies and any violations of the checked dependencies will be indicated.

Abstract: Generating a hardware description for a programmable hardware element based on a graphical program including multiple models of computation. A graphical program may be received which includes a first portion having a first computational model and a second portion having a second computational model. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be configured to configure a programmable hardware element to implement functionality of the graphical program.

Abstract: Embodiments relate to systems and methods for application development using middleware. A developer can launch a development request from a client or local network to a remote development server, thereby invoking a set of frameworks and other tools to carry out a desired application build. The development request can specify the type or configuration of the desired application, such as, for example, email, spreadsheet, media playback, or other applications, along with parameters such as target operating systems. The user can assemble desired code from libraries stored in the virtualized middleware framework, and debug the application build against a set of data sources aggregated by the development server. A developer can therefore leverage rapid application development tools at the middleware, without a necessity to invest in local development tools or separately build or locate test data sources.

Abstract: Mechanisms for development tooling enablement of audit event generation are provided. The mechanisms automatically generate and insert compliance audit record generation code where appropriate in identified portions of program instructions based on established compliance policies and labels associated with keywords/library functions appearing in the source code. The mechanisms may analyze the program instructions to identify at least one portion of program instructions meeting a compliance policy requirement for generation of a compliance audit record. Compliance audit record generation code for generating the compliance audit record may be generated. The compliance audit record generation code may be inserted into the at least one portion of program instructions to generate modified program instructions. The modified program instructions may be output for execution on a computing device.

Abstract: A system and method for visually indicating one or more problems in a graphical program. The graphical program may be programmatically analyzed to discover a problem (or potential problem) in the graphical program. The problem found during the programmatic analysis of the graphical program may then be visually indicated on a display device. Visually indicating the problem may comprise visually indicating one or more objects in the graphical program to which the problem corresponds. Visually indicating the graphical program object(s) may comprise displaying information or altering the appearance of the object(s) in order to call the user's attention to the object(s).

Abstract: A system described herein includes a receiver component that receives third party code for execution in a host environment, wherein the third party code corresponds to a dynamic programming language, and wherein the third party code has at least one object reference to a first object that is used by the third party code. A detouring component automatically replaces the first object referenced by the third party code with a proxy object such that the third party code at runtime calls the proxy object instead of the first object.

Abstract: A mechanism for providing a source code control system that employs test case execution results to mandate that software code have a specific level of quality for check-in to a central repository. A request to check-in a modified copy of a source code file to a repository is received, wherein the modified copy comprises changes to the source code file located in the repository. The modified copy of the source code file is placed in a quality check pending state in the repository. Responsive to an occurrence of a specific event or expiration of a set time period, applicable regression test cases are executed against the changes in the modified copy. A determination is made as to whether the regression test cases are successful. If the regression test cases are successful, the changes in the modified copy are committed to the source code file located in the repository.

Abstract: Dynamic test coverage to evaluate an artifact code is provided. Code of an artifact to be tested is identified. The code coverage of the test code is analyzed. The current coverage information is stored. Code coverage information for one or more prior versions of the test code is retrieved. The current coverage information is compared with the prior coverage information. Responsive to a determination that a difference between the current coverage information and the prior coverage information exists, the difference is collected. Responsive to a determination that test cases are to be generated automatically, generating, automatically, new test cases based on the difference. The new test cases are stored. Code coverage of the test code is analyzed based on the new test case. The new coverage information is stored. The new coverage information is sent to the user.

Abstract: A system and method for visually indicating one or more problems in a graphical program. The graphical program may be programmatically analyzed to discover a problem (or potential problem) in the graphical program. The problem found during the programmatic analysis of the graphical program may then be visually indicated on a display device. Visually indicating the problem may comprise visually indicating one or more objects in the graphical program to which the problem corresponds. Visually indicating the graphical program object(s) may comprise displaying information or altering the appearance of the object(s) in order to call the user's attention to the object(s).

Abstract: In an embodiment, a computer system initiates an application debugging process for an application that is to be debugged and maps runtime object elements of the application to both code elements and graphical elements. The computer system appends portions of software code to each runtime object element so that a runtime event is outputted indicating which corresponding graphical or code element is currently being processed. The computer system accesses the outputted runtime events to determine which graphical or code element is currently being processed and, based on the accessed outputted runtime events and based on the mappings, displays the elements currently being debugged in a first view. The computer system, based on the accessed outputted runtime events and based on the mappings, switches views from the first view to a second view without restarting the application debugging process for the application being debugged.

Abstract: Methods and apparatuses for approximate functional matching are described including identifying functionally similar subsets of an integrated circuit design or software program, distinguishing control inputs of the subsets from data inputs, and assigning combinations of logic values to the input control signals to capture co-factors for functional matching.

Abstract: An apparatus and a method for Java array interception using bytecode manipulation and data flow analysis. In one embodiment, a user-provided object class is identified. An array access operation of the user-provided object class is intercepted. The intercepted array access operation is translated with an emulator class of a native Java array. The translated array access operation is sent to an emulator class to determine whether to dispatch to the native Java array or an alternate data source.

Abstract: A test coverage analysis method and corresponding apparatus are disclosed, wherein, by executing the program under test using one or more test cases, generating one or more heapdump files containing the call stack information of the program under test, and analyzing the call stack information in the one or more heapdump files, the coverage information of the one or more test cases in terms of functions in the program under test is obtained.

Abstract: Disclosed herein are systems, methods, and computer readable-media for obfuscating code. The method includes extracting a conditional statement from a computer program, creating a function equivalent to the conditional statement, creating a pointer that points to the function, storing the pointer in an array of pointers, replacing the conditional statement with a call to the function using the pointer at an index in the array, and during runtime of the computer program, dynamically calculating the index corresponding to the pointer in the array. In one aspect, a subset of instructions is extracted from a path associated with the conditional statement and the subset of instructions is placed in the function to evaluate the conditional statement. In another aspect, the conditional statement is replaced with a call to a select function that (1) calculates the index into the array, (2) retrieves the function pointer from the array using the index, and (3) calls the function using the function pointer.

Abstract: A distributed processor-based system comprises a plurality of communicating platforms, wherein a number of platforms in the distributed processor-based system comprise at least one compiler, the at least one compiler being operably coupled to data type translation logic and arranged to generate a memory layout for the respective platform. In response to an indication for a communication to occur between a first platform and a second platform the data type translation logic translates a memory layout using data type attributes for data to be transferred from the first platform to the second platform based on at least one platform-specific characteristic, such that the data does not require translating when received at the second platform.

Abstract: Disclosed herein are systems, methods, and computer readable-media for obfuscating code through conditional expansion obfuscation. The method includes identifying a conditional expression in a computer program, identifying a sequence of conditional expressions that is semantically equivalent to the conditional expression, and replacing the conditional expression with the semantically equivalent sequence of conditional expressions. One option replaces each like conditional expression in the computer program with a diverse set of sequences of semantically equivalent conditional expressions. A second option rearranges computer instructions that are to be processed after the sequence of conditional expression is evaluated so that a portion of the instructions is performed before the entire sequence of conditional expressions is evaluated. A third option performs conditional expansion obfuscation of a conditional statement in combination with branch extraction obfuscation.

Abstract: The efficient use of type descriptors with frozen objects. A frozen object might actually include several type descriptors, a primary type descriptor that is canonical according to a set of canonicalization rules, and an auxiliary type descriptor that is not identical to the primary type descriptor. The auxiliary type descriptor may be used to access the canonical type descriptor. When performing an operation, if the auxiliary type descriptor can be used to perform the operation, then that auxiliary type descriptor may be used. If the canonical type descriptor is to be used to perform the operation, the auxiliary type descriptor is used to gain access to the canonical primary type descriptor. The primary type descriptor is then used to perform the operation.

Abstract: Described herein is a method and apparatus for generating automatic language bindings. The method includes receiving a request for a first program module in a first language from a second program in a second language. A binding module is created in the second language in response to the request, where the binding module is generated from debug data of the first program module. The the binding module is returned to the second program module. The second program module can then access the functionality of the first program module through use of the functions of the binding module.

Abstract: Firmware updates at an information handling system flash memory device, such as provisioning information stored on a USB device, are securely performed by using a buffer memory and a secured code. An application running on a CPU generates a firmware update and a security code, such as a ciphered hash code based on the firmware update, stores the firmware update and security code in a buffer, and informs a management processor of the update. The management processor analyzes the firmware update to authorize copying of the update from the buffer to the flash memory device. For instance, the management processor creates the security code from the firmware update and compares the created code with the security code stored in the buffer to validate the firmware update.

Abstract: A provisioning server can actively monitor the software provisioning processes being performed on a target machine to determine the status and integrity of the provisioning processes and notify an administrator or user of the status and integrity. The provisioning server can be configured to include a monitoring module and a message module. The monitoring module can be configured to monitor software provisioning processes being performed on a target machine and determine the status and integrity of the provisioning processes. The message module can be configured send notification to the administrator or user of the status and integrity of the provisioning processes.