With Pretreatment Or Preparation Of A Base (e.g., Annealing) Patents (Class 117/106)
  • Patent number: 9418840
    Abstract: Silicon-containing gas, carbon-containing gas, and chlorine-containing gas are introduced into a reacting furnace. Next, a SiC epitaxial film is grown on the front surface of a 4H-SiC substrate by a halide CVD method in a mixed gas atmosphere made of the plurality of gasses introduced. In the SiC epitaxial film growing, a SiC epitaxial film of a first predetermined thickness is grown at a first growth rate. The first growth rate is increased from an initial growth rate to a higher growth rate. Furthermore, the SiC epitaxial film is grown, at a second growth rate, until the thickness of the SiC epitaxial film reaches a second predetermined thickness. By so doing, it is possible to improve the crystallinity of a silicon carbide semiconductor film grown in a gas atmosphere containing halide.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: August 16, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki Kawada, Yoshiyuki Yonezawa
  • Patent number: 9412896
    Abstract: To reduce degradation, by the LID effect, of the conversion efficiency of photovoltaic cells made of crystalline silicon, one or more steps of controlled introduction of voids into the silicon are carried out by one or more steps chosen from among: siliciding, nitriding, ion implantation, laser irradiation, mechanical bending stress applied on one face of the silicon substrate, in combination with a temperature promoting the formation of voids in the substrate. These voids make it possible to reduce the level of interstitial oxygen by an effect of diffusion of VO complexes and precipitation of oxygen. The introduction of voids has the other effect of reducing the level of autointerstitials, and therefore of limiting the formation of interstitial boron. The phenomena of LID by activation of BiOi2 complexes are thus limited. This applies notably to photovoltaic cells based on monocrystalline or polycrystalline silicon having a high concentration of boron and oxygen.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: August 9, 2016
    Assignee: Commissariat A L'Energie Atomique et aux Alternatives
    Inventors: Pascal Pochet, Sébastien Dubois
  • Patent number: 9378950
    Abstract: A method for removing nuclei formed during a selective epitaxial growth process includes epitaxially growing a first group of one or more semiconductor structures over a substrate with one or more mask layers. A second group of a plurality of semiconductor structures is formed on the one or more mask layers. The method also includes forming one or more protective layers over the first group of one or more semiconductor structures. At least a subset of the second group of the plurality of semiconductor structures is exposed from the one or more protective layers. The method further includes, subsequent to forming the one or more protective layers over the first group of one or more semiconductor structures, etching at least the subset of the second group of the plurality of semiconductor structures.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: June 28, 2016
    Assignees: STRATIO, STRATIO INC.
    Inventors: Jae Hyung Lee, Youngsik Kim, Yeul Na, Woo-Shik Jung
  • Patent number: 9287121
    Abstract: A method of manufacturing a SiC epitaxial wafer wherein a SiC epitaxial layer is provided on a SiC single crystal substrate having an off angle. The method includes determining a ratio of basal plane dislocations (BPD) which cause stacking faults in a SiC epitaxial film of a prescribed thickness, to basal plane dislocations which are present on a growth surface of the SiC single crystal substrate, determining an upper limit of surface density of basal plane dislocations, preparing a SiC single crystal substrate which has surface density equal to or less than the above upper limit, and forming a SiC epitaxial film on the SiC single crystal substrate under the same conditions as the growth conditions of the epitaxial film used in the step of determining the ratio.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: March 15, 2016
    Assignee: SHOWA DENKO K.K.
    Inventors: Kenji Momose, Michiya Odawara, Daisuke Muto, Yoshiaki Kageshima
  • Patent number: 9153473
    Abstract: Methods for forming a device are presented. A substrate having top and bottom pad stacks is provided. Each pad stack includes at least first and second pad layers. The second pad layers of the top and bottom pad stacks include an initial thickness TT1 and TB1 respectively. Trench isolation regions are formed in the substrate. The second pad layer of the top and bottom pad stacks are removed after forming the trench isolation regions by a batch wet etch process.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: October 6, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Liang Li, Wei Lu
  • Patent number: 9039834
    Abstract: Non-polar (11 20) a-plane gallium nitride (GaN) films with planar surfaces are grown on (1 102) r-plane sapphire substrates by employing a low temperature nucleation layer as a buffer layer prior to a high temperature growth of the non-polar (11 20) a-plane GaN thin films.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: May 26, 2015
    Assignee: The Regents of the University of California
    Inventors: Michael D. Craven, James Stephen Speck
  • Publication number: 20150115771
    Abstract: An elastic wave device includes a piezoelectric substrate including a primary surface and a first electrode which is provided on the primary surface of the piezoelectric substrate, which includes a first multilayer metal film including at least three metal films laminated in a bottom-to-top direction, and which includes at least an IDT film. The first multilayer metal film includes a Ti film as the topmost film and has a crystal orientation oriented in a predetermined direction so that the normal line direction of the plane of a Ti crystal of the Ti film coincides with the Z axis of a crystal of a piezoelectric body defining the piezoelectric substrate.
    Type: Application
    Filed: October 9, 2014
    Publication date: April 30, 2015
    Inventor: Chihiro KONOMA
  • Publication number: 20150096488
    Abstract: The present disclosure generally relates to systems and methods for growing and preferentially volumetrically enhancing group III-V nitride crystals. In particular the systems and methods include diffusing constituent species of the crystals through a porous body composed of the constituent species, where the species freely nucleate to grow large nitride crystals. The systems and methods further include using thermal gradients and/or chemical driving agents to enhance or limit crystal growth in one or more planes.
    Type: Application
    Filed: October 8, 2014
    Publication date: April 9, 2015
    Inventors: Peng Lu, Jason Schmitt
  • Patent number: 8986464
    Abstract: A semiconductor substrate includes: single crystal silicon; a mask material formed on a surface of the single crystal silicon and having an opening; a silicon carbide film formed on a portion exposed in the opening of the single crystal silicon; and a single crystal silicon carbide film formed so as to cover the silicon carbide film and the mask material. The mask material has a viscosity of 105 Pa·S or more and 1014.5 Pa·S or less in a temperature range of 950 to 1400° C.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Yukimune Watanabe
  • Publication number: 20150054134
    Abstract: A method of manufacturing a silicon wafer provides a silicon wafer which can reduce the precipitation of oxygen to prevent a wafer deformation from being generated and can prevent a slip extension due to boat scratches and transfer scratches serving as a reason for a decrease in wafer strength, even when the wafer is provided to a rapid temperature-rising-and-falling thermal treatment process.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 26, 2015
    Applicant: SUMCO CORPORATION
    Inventors: Toshiaki ONO, Wataru ITO, Jun FUJISE
  • Patent number: 8945302
    Abstract: Method for crystal growth from a surfactant of a metal-nonmetal (MN) compound, including the procedures of providing a seed crystal, introducing atoms of a first metal to the seed crystal thus forming a thin liquid metal wetting layer on a surface of the seed crystal, setting a temperature of the seed crystal below a minimal temperature required for dissolving MN molecules in the wetting layer and above a melting point of the first metal, each one of the MN molecules being formed from an atom of a second metal and an atom of a first nonmetal, introducing the MN molecules which form an MN surfactant monolayer, thereby facilitating a formation of the wetting layer between the MN surfactant monolayer and the surface of the seed crystal, and regulating a thickness of the wetting layer, thereby growing an epitaxial layer of the MN compound on the seed crystal.
    Type: Grant
    Filed: March 4, 2012
    Date of Patent: February 3, 2015
    Assignee: Mosaic Crystals Ltd.
    Inventor: Moshe Einav
  • Patent number: 8945304
    Abstract: A system and method A method of growing an elongate nanoelement from a growth surface includes: a) cleaning a growth surface on a base element; b) providing an ultrahigh vacuum reaction environment over the cleaned growth surface; c) generating a reactive gas of an atomic material to be used in forming the nanoelement; d) projecting a stream of the reactive gas at the growth surface within the reactive environment while maintaining a vacuum of at most 1×10?4 Pascal; e) growing the elongate nanoelement from the growth surface within the environment while maintaining the pressure of step c); f) after a desired length of nanoelement is attained within the environment, stopping direction of reactive gas into the environment; and g) returning the environment to an ultrahigh vacuum condition.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: February 3, 2015
    Assignee: The Board of Regents of the Nevada System of Higher Education on behalf of the University of Nevada, Las Vegas University of Nevada
    Inventors: Biswajit Das, Myung B. Lee
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Publication number: 20150020731
    Abstract: Bulk single crystal of aluminum nitride (AlN) having an areal planar defect density?100 cm?2. Methods for growing single crystal aluminum nitride include melting an aluminum foil to uniformly wet a foundation with a layer of aluminum, the foundation forming a portion of an AlN seed holder, for an AlN seed to be used for the AlN growth. The holder may consist essentially of a substantially impervious backing plate.
    Type: Application
    Filed: August 13, 2014
    Publication date: January 22, 2015
    Inventors: Robert T. Bondokov, Kenneth E. Morgan, Leo J. Schowalter, Glen A. Stack
  • Publication number: 20150024223
    Abstract: The present invention provides a monolithic integrated lattice mismatched crystal template and a preparation method thereof by using low-viscosity material, the preparation method for the crystal template includes: providing a first crystal layer with a first lattice constant; growing a buffer layer on the first crystal layer; below the melting point of the buffer layer, growing a second crystal layer and a template layer by sequentially performing the growth process of a second crystal layer and the growth process of a first template layer on the buffer layer, or growing a template layer by directly performing a first template layer growth process on the buffer layer; melting and converting the buffer layer to an amorphous state, performing a second template layer growth process on the template layer grown by the first template layer growth process at the growth temperature above the glass transition temperature of the buffer layer, sequentially growing a template layer until the lattice of the template laye
    Type: Application
    Filed: April 6, 2012
    Publication date: January 22, 2015
    Applicant: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY
    Inventor: Shumin Wang
  • Patent number: 8936682
    Abstract: A manufacturing method of a SiC single crystal includes growing a SiC single crystal on a surface of a SiC seed crystal, which satisfies following conditions: (i) the SiC seed crystal includes a main growth surface composed of a plurality of sub-growth surfaces; (ii) among directions from an uppermost portion of a {0001} plane on the main growth surface to portions on a periphery of the main growth surface, the SiC seed crystal has a main direction in which a plurality of sub-growth surfaces is arranged; and (iii) an offset angle ?k of a k-th sub-growth surface and an offset angle ?k+1 of a (k+1)-th sub-growth surface satisfy a relationship of ?k<?k+1.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: January 20, 2015
    Assignee: DENSO CORPORATION
    Inventors: Yasushi Urakami, Itaru Gunjishima, Ayumu Adachi
  • Patent number: 8936681
    Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A carbon nanotube layer is placed on the epitaxial growth surface. An epitaxial layer is epitaxially grown on the epitaxial growth surface. The carbon nanotube layer is removed. The carbon nanotube layer can be removed by heating.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: January 20, 2015
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Publication number: 20150017466
    Abstract: A self-aligned tunable metamaterial is formed as a wire mesh. Self-aligned channel grids are formed in layers in a silicon substrate using deep trench formation and a high-temperature anneal. Vertical wells at the channels may also be etched. This may result in a three-dimensional mesh grid of metal and other material. In another embodiment, metallic beads are deposited at each intersection of the mesh grid, the grid is encased in a rigid medium, and the mesh grid is removed to form an artificial nanocrystal.
    Type: Application
    Filed: March 11, 2013
    Publication date: January 15, 2015
    Inventors: Arturo A. Ayon, Ramakrishna Kotha, Diana Strickland
  • Publication number: 20150004435
    Abstract: The present invention relates to a method for growing a non-polar m-plane epitaxial layer on a single crystal oxide substrate, which comprises the following steps: providing a single crystal oxide with a perovskite structure; using a plane of the single crystal oxide as a substrate; and forming an m-plane epitaxial layer of wurtzite semiconductors on the plane of the single crystal oxide by a vapor deposition process, wherein the non-polar m-plane epitaxial layer may be GaN, or III-nitrides. The present invention also provides an epitaxial layer having an m-plane obtained according to the aforementioned method.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 1, 2015
    Inventors: Li CHANG, Yen-Teng HO
  • Patent number: 8920560
    Abstract: A method for manufacturing an epitaxial wafer includes: a step of pulling a single crystal from a boron-doped silicon melt in a chamber based on a Czochralski process; and a step of forming an epitaxial layer on a surface of a silicon wafer sliced from the single crystal. The single crystal is allowed to grow while passed through a temperature region of 800 to 600° C. in the chamber in 250 to 180 minutes during the pulling step. The grown single crystal has an oxygen concentration of 10×1017 to 12×1017 atoms/cm3 and a resistivity of 0.03 to 0.01 ?cm. The silicon wafer is subjected to pre-annealing prior to the step of forming the epitaxial layer on the surface of the silicon wafer, for 10 minutes to 4 hours at a predetermined temperature within a temperature region of 650 to 900° C. in an inert gas atmosphere. The method is to fabricate an epitaxial wafer that has a diameter of 300 mm or more, and that attains a high IG effect, and involves few epitaxial defects.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: December 30, 2014
    Assignee: Sumco Corporation
    Inventors: Yasuo Koike, Toshiaki Ono, Naoki Ikeda, Tomokazu Katano
  • Patent number: 8906487
    Abstract: In a base material with a single-crystal silicon carbide film according to an embodiment of the invention, a plurality of recessed portions is formed on the surface of a silicon substrate, an insulating film including silicon oxide is formed across the surface of the silicon substrate including the inner surfaces of the recessed portions, the top surfaces of side wall portions of recessed portions of the insulating film form flat surfaces, a single-crystal silicon carbide film is joined on the flat surfaces, and the recessed portions below the single-crystal silicon carbide film form holes.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 9, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Shimada
  • Publication number: 20140345517
    Abstract: A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Inventor: Qing Liu
  • Publication number: 20140338589
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 20, 2014
    Inventors: Christopher Leitz, Christopher J. Vineis, Richard Westhoff, Vicky Yang, Matthew T. Currie
  • Patent number: 8888914
    Abstract: The object is to provide a photoelectric surface member which allows higher quantum efficiency. In order to achieve this object, a photoelectric surface member 1a is a crystalline layer formed by a nitride type semiconductor material, and comprises a nitride semiconductor crystal layer 10 where the direction from the first surface 101 to the second surface 102 is the negative c polar direction of the crystal, an adhesive layer 12 formed along the first surface 101 of the nitride semiconductor crystal layer 10, and a glass substrate 14 which is adhesively fixed to the adhesive layer 12 such that the adhesive layer 12 is located between the glass substrate 14 and the nitride semiconductor crystal layer 10.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: November 18, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Tokuaki Nihashi, Masatomo Sumiya, Minoru Hagino, Shunro Fuke
  • Publication number: 20140332915
    Abstract: Direct growth of graphene on Co3O4(111) at 1000 K was achieved by molecular beam epitaxy from a graphite source. Auger spectroscopy shows a characteristic sp2 carbon lineshape, at average carbon coverages from 0.4-3 monolayers. Low energy electron diffraction (LEED) indicates (111) ordering of the sp2 carbon film with a lattice constant of 2.5 (±0.1) ? characteristic of graphene. Six-fold symmetry of the graphene diffraction spots is observed at 0.4, 1 and 3 monolayers. The LEED data also indicate an average domain size of ˜1800 ?, and show an incommensurate interface with the Co3O4(111) substrate, where the latter exhibits a lattice constant of 2.8 (±0.1) ?. Core level photoemission shows a characteristically asymmetric C(1s) feature, with the expected lr to lr* satellite feature, but with a binding energy for the three monolayer film of 284.9 (±0.1) eV, indicative of substantial graphene-to-oxide charge transfer.
    Type: Application
    Filed: December 6, 2012
    Publication date: November 13, 2014
    Applicant: University of North Texas
    Inventor: Jeffry A. Kelber
  • Patent number: 8882909
    Abstract: Relaxed germanium buffer layers can be grown economically on misoriented silicon wafers by low-energy plasma-enhanced chemical vapor deposition. In conjunction with thermal annealing and/or patterning, the buffer layers can serve as high-quality virtual substrates for the growth of crack-free GaAs layers suitable for high-efficiency solar cells, lasers and field effect transistors.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: November 11, 2014
    Assignee: Dichroic Cell S.R.L.
    Inventor: Hans Von Kaenel
  • Patent number: 8876973
    Abstract: There is provided an n type (100) oriented single crystal diamond semiconductor film into which phosphorous atoms have been doped and a method of producing the same. The n type (100) oriented single crystal diamond semiconductor film, characterized in that (100) oriented diamond is epitaxially grown on a substrate under such conditions that; the diamond substrate is (100) oriented diamond, a means for chemical vapor deposition provides hydrogen, hydrocarbon and a phosphorous compound in the plasma vapor phase, the ratio of phosphorous atoms to carbon atoms in the plasma vapor phase is no less than 0.1%, and the ratio of carbon atoms to hydrogen atoms is no less than 0.05%, and the method of producing the same.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: November 4, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Hiromitsu Kato, Satoshi Yamasaki, Hideyo Ookushi, Shinichi Shikata
  • Patent number: 8852342
    Abstract: A surface of a single crystalline semiconductor-carbon alloy layer having a surface normal along or close to a major crystallographic direction is provided by mechanical means such as cutting and/or polishing. Such a surface has naturally formed irregular surface features. Small semiconductor islands are deposited on the surface of single crystalline semiconductor-carbon alloy layer. Another single crystalline semiconductor-carbon alloy structure may be placed on the small semiconductor islands, and the assembly of the two semiconductor-carbon alloy layers with the semiconductor islands therebetween is annealed. During the initial phase of the anneal, surface diffusion of the semiconductor material proceeds to form vicinal surfaces while graphitization is suppressed because the space between the two semiconductor-carbon alloy layers maintains a high vapor pressure of the semiconductor material.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christos D. Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Robert L. Wisnieff
  • Publication number: 20140291811
    Abstract: A group III nitride crystal substrate is provided in which a uniform distortion at a surface layer of the crystal substrate represented by a value of |d1?d2|/d2 obtained from a plane spacing d1 at the X-ray penetration depth of 0.3 ?m and a plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 1.9×10?3, and the main surface has a plane orientation inclined in the <10-10> direction at an angle equal to or greater than 10° and equal to or smaller than 80° with respect to one of (0001) and (000-1) planes of the crystal substrate. A group III nitride crystal substrate suitable for manufacturing a light emitting device with a blue shift of an emission suppressed, an epilayer-containing group III nitride crystal substrate, a semiconductor device and a method of manufacturing the same can thereby be provided.
    Type: Application
    Filed: June 13, 2014
    Publication date: October 2, 2014
    Inventors: Keiji ISHIBASHI, Yusuke YOSHIZUMI
  • Publication number: 20140291694
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.
    Type: Application
    Filed: June 16, 2014
    Publication date: October 2, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Publication number: 20140290566
    Abstract: Disclosed is a process of surface treatment of a substrate. The method of treating a surface of a substrate comprises preparing the substrate, and performing an etching process with respect to a surface of the substrate. The etching process comprises a step of introducing etching gas to the surface of the substrate, and the etching gas comprises a halogen compound and a silane compound.
    Type: Application
    Filed: August 21, 2012
    Publication date: October 2, 2014
    Applicant: LG INNOTEK CO., LTD.
    Inventor: Heung Teak Bae
  • Publication number: 20140291810
    Abstract: The present invention relates to a method for manufacturing semiconductor materials comprising epitaxial growing of group III-V materials, for example gallium arsenide (GaAs), on for example a non III-V group material like silicon (Si) substrates (wafers), and especially to pre-processing steps providing a location stabilisation of dislocation faults in a surface layer of the non III-V material wafer in an orientation relative to an epitaxial material growing direction during growing of the III-V materials, wherein the location stabilised dislocation fault orientations provides a barrier against threading dislocations (stacking of faults) from being formed in the growing direction of the III-V materials during the epitaxial growth process.
    Type: Application
    Filed: August 22, 2012
    Publication date: October 2, 2014
    Applicant: Integrated Optoelectronics AS
    Inventors: Renato Bugge, Geir Myrvagnes, Tron Arne Nilsen
  • Patent number: 8840723
    Abstract: An apparatus for manufacturing polycrystalline silicon whereby raw-material gas is supplied to one or more heated silicon seed rods provided vertically in a reactor so as to deposit the polycrystalline silicon on a surface of the silicon seed rod, having a seed rod holding member, made of conductive material, having a holding hole in which a lower end of the silicon seed rod is inserted, the holding hole having a horizontal cross-sectional shape with at least two corners, and the holding member having a screw hole extending from the outer surface of the seed rod holding member to at least the holding hole and formed at the location of at least two corners of the holding hole; and a fixing screw which fixes the silicon seed rod and is threaded through at least one of the screw holes.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: September 23, 2014
    Assignee: Mitsubishi Materials Corporation
    Inventors: Toshihide Endoh, Masayuki Tebakari, Toshiyuki Ishii, Masaaki Sakaguchi
  • Publication number: 20140272335
    Abstract: A bi-layer seed layer can exhibit good seed property for an infrared reflective layer, together with improved thermal stability. The bi-layer seed layer can include a thin zinc oxide layer having a desired crystallographic orientation for a silver infrared reflective layer disposed on a bottom layer having a desired thermal stability. The thermal stable layer can include aluminum, magnesium, or bismuth doped tin oxide (AlSnO, MgSnO, or BiSnO), which can have better thermal stability than zinc oxide but poorer lattice matching for serving as a seed layer template for silver (111).
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Applicant: INTERMOLECULAR INC.
    Inventor: INTERMOLECULAR INC.
  • Publication number: 20140251205
    Abstract: A system for depositing a film on a substrate comprises a lateral control shutter disposed between the substrate and a material source. The lateral control shutter is configured to block some predetermined portion of source material to prevent deposition of source material onto undesirable portion of the substrate. One of the lateral control shutter or the substrate moves with respect to the other to facilitate moving a lateral growth boundary originating from one or more seed crystals. A lateral epitaxial deposition across the substrate ensues, by having an advancing growth front that expands grain size and forms a single crystal film on the surface of the substrate.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: Tivra Corporation
    Inventor: Indranil De
  • Publication number: 20140190402
    Abstract: Disclosed are an apparatus and a method for fabricating an ingot. The apparatus includes a crucible receiving source materials therein; a holder fixing a seed located above the source materials; and an adhesive layer interposed between the holder and the seed and chemically bonded to the seed.
    Type: Application
    Filed: June 1, 2012
    Publication date: July 10, 2014
    Applicant: LG INNOTEK CO., LTD.
    Inventor: Dong Geun Shin
  • Patent number: 8771552
    Abstract: A group III nitride crystal substrate is provided in which a uniform distortion at a surface layer of the crystal substrate represented by a value of |d1 ?d2 |/d2 obtained from a plane spacing d1 at the X-ray penetration depth of 0.3 ?m and a plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 1.9 ×10?3, and the main surface has a plane orientation inclined in the <10-10> direction at an angle equal to or greater than 10° and equal to or smaller than 80° with respect to one of (0001) and (000-1) planes of the crystal substrate. A group III nitride crystal substrate suitable for manufacturing a light emitting device with a blue shift of an emission suppressed, an epilayer-containing group III nitride crystal substrate, a semiconductor device and a method of manufacturing the same can thereby be provided.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: July 8, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Yusuke Yoshizumi
  • Patent number: 8728237
    Abstract: A method for growing nitride semiconductor crystals contains: growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate at a first growth temperature, using a first carrier gas containing an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer at a second growth temperature higher than the first growth temperature, using a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer at the second growth temperature, using a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonari Shioda, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
  • Patent number: 8728622
    Abstract: Provided is a base substrate with which a Group-III nitride crystal having a large area and a large thickness can be grown while inhibiting crack generation. A single-crystal substrate for use in growing a Group-III nitride crystal thereon, which satisfies the following expression (1), wherein Z1 (?m) is an amount of warpage of physical shape in a growth surface of the single-crystal substrate and Z2 (?m) is an amount of warpage calculated from a radius of curvature of crystallographic-plane shape in a growth surface of the single-crystal substrate: ?40<Z2/Z1<?1: Expression (1).
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: May 20, 2014
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Kenji Fujito, Yasuhiro Uchiyama
  • Patent number: 8728235
    Abstract: A manufacturing method for three-dimensional GaN epitaxial structure comprises a disposing step, in which a substrate of LiAlO2 and a source metal of Ga are disposed inside an vacuum chamber. An exposing step is importing N ions in plasma state and generated by a nitrogen source into the chamber. A heating step is heating up the source metal to generate Ga vapor. A growing step is forming a three-dimensional GaN epitaxial structure with hexagonal micropyramid or hexagonal rod having a broadened disk-like surface on the substrate by reaction between the Ga vapor and the plasma state of N ions.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: May 20, 2014
    Assignee: National Sun Yat-Sen University
    Inventors: I-Kai Lo, Chia-Ho Hsieh, Yu-Chi Hsu, Wen-Yuan Pang, Ming-Chi Chou
  • Publication number: 20140116329
    Abstract: A method is disclosed for making sapphire glass, consisting of a layer of sapphire on glass. The sapphire layer, or crystalline Al2O3, is deposited on ordinary (soda-lime) glass via a textured MgO template.
    Type: Application
    Filed: January 2, 2014
    Publication date: May 1, 2014
    Applicant: SOLAR-TECTIC LLC
    Inventors: Karin Chaudhari, Pia Chaudhari, Ashok Chaudhari
  • Publication number: 20140106182
    Abstract: A sub-structure, suitable for use as a hot seed on which to form a perpendicular magnetic main write pole, is described. It is made up of a buffer layer of atomic layer deposited alumina on which there are one or more seed layers having a body-centered cubic (bcc) crystal structure. Finally, the high coercivity magnetic film lies on the seed layer(s). It is critical that the high coercivity magnetic film be deposited at a very low deposition rate (around 1 Angstrom per second).
    Type: Application
    Filed: October 14, 2012
    Publication date: April 17, 2014
    Applicant: HEADWAY TECHNOLOGIES, INC.
    Inventors: Shengyuan Wang, Kunliang Zhang, Min Li
  • Patent number: 8673074
    Abstract: A method of growing planar non-polar m-plane or semi-polar III-Nitride material, such as an m-plane gallium nitride (GaN) epitaxial layer, wherein the III-Nitride material is grown on a suitable substrate, such as an m-plane sapphire substrate, using hydride vapor phase epitaxy (HVPE). The method includes in-situ pretreatment of the substrate at elevated temperatures in an atmosphere of ammonia and argon, growing an intermediate layer such as an aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN) on the annealed substrate, and growing the non-polar m-plane III-Nitride epitaxial layer on the intermediate layer using HVPE.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: March 18, 2014
    Assignee: Ostendo Technologies, Inc.
    Inventors: Alexander Usikov, Alexander Syrkin, Robert G. W. Brown, Hussein S. El-Ghoroury, Philippe Spiberg, Vladimir Ivantsov, Oleg Kovalenkov, Lisa Shapovalova
  • Publication number: 20140048013
    Abstract: Zinc oxide layer, including pure zinc oxide and doped zinc oxide, can be deposited with preferred crystal orientation and improved electrical conductivity by employing a seed layer comprising a metallic element. By selecting metallic elements that can easily crystallized at low temperature on glass substrates, together with possessing preferred crystal orientations and sizes, zinc oxide layer with preferred crystal orientation and large grain size can be formed, leading to potential optimization of transparent conductive oxide layer stacks.
    Type: Application
    Filed: August 17, 2012
    Publication date: February 20, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Guowen Ding, Hien Minh Huu Le, Zhi-Wen Sun
  • Patent number: 8652255
    Abstract: A method of: flowing a silicon source gas, a carbon source gas, and a carrier gas into a growth chamber under growth conditions to epitaxial grow silicon carbide on a wafer in the growth chamber; stopping or reducing the flow of the silicon source gas to interrupt the silicon carbide growth and maintaining the flow of the carrier gas while maintaining an elevated temperature in the growth chamber for a period of time; and resuming the flow of the silicon source gas to reinitiate silicon carbide growth. The wafer remains in the growth chamber throughout the method.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: February 18, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Robert E Stahlbush, Brenda L VanMil, Kok-Keong Lew, Rachael L Myers-Ward, David Kurt Gaskill, Charles R. Eddy, Jr.
  • Patent number: 8647435
    Abstract: HVPE reactors and methods for growth of p-type group III nitride materials including p-GaN. A reaction product such as gallium chloride is delivered to a growth zone inside of a HVPE reactor by a carrier gas such as Argon. The gallium chloride reacts with a reactive gas such as ammonia in the growth zone in the presence of a magnesium-containing gas to grow p-type group III nitride materials. The source of magnesium is an external, non-metallic compound source such as Cp2Mg.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: February 11, 2014
    Assignee: Ostendo Technologies, Inc.
    Inventors: Vladimir A. Dmitriev, Oleg V. Kovalenkov, Vladimir Ivantsov, Lisa Shapovalov, Alexander L. Syrkin, Anna Volkova, Vladimir Sizov, Alexander Usikov, Vitali A. Soukhoveev
  • Patent number: 8647436
    Abstract: Isotopically-enriched graphene and isotope junctions are epitaxially grown on a catalyst substrate using a focused carbon ion beam technique. The focused carbon ion beam is filtered to pass substantially a single ion species including a single desired carbon isotope. The ion beam and filtering together provide a means to selectively isotopically-enrich the epitaxially-grown graphene from given carbon precursor and to selectively deposit graphene enriched with different carbon isotopes in different regions.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: February 11, 2014
    Assignees: Raytheon Company, The Arizona Board of Regents
    Inventors: Delmar L. Barker, William R. Owens, John Warren Beck
  • Patent number: 8624266
    Abstract: A main surface of a silicon carbide substrate is inclined by an off angle in an off direction from {0001} plane of a hexagonal crystal. The main surface has such a characteristic that, among emitting regions emitting photoluminescent light having a wavelength exceeding 650 nm of the main surface caused by excitation light having higher energy than band-gap of the hexagonal silicon carbide, the number of those having a dimension of at most 15 ?m in a direction perpendicular to the off direction and a dimension in a direction parallel to the off direction not larger than a value obtained by dividing penetration length of the excitation light in the hexagonal silicon carbide by a tangent of the off angle is at most 1×104 per 1 cm2. Accordingly, reverse leakage current can be reduced.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: January 7, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Tsubasa Honke
  • Publication number: 20130333613
    Abstract: Method for crystal growth from a surfactant of a metal-nonmetal (MN) compound, including the procedures of providing a seed crystal, introducing atoms of a first metal to the seed crystal thus forming a thin liquid metal wetting layer on a surface of the seed crystal, setting a temperature of the seed crystal below a minimal temperature required for dissolving MN molecules in the wetting layer and above a melting point of the first metal, each one of the MN molecules being formed from an atom of a second metal and an atom of a first nonmetal, introducing the MN molecules which form an MN surfactant monolayer, thereby facilitating a formation of the wetting layer between the MN surfactant monolayer and the surface of the seed crystal, and regulating a thickness of the wetting layer, thereby growing an epitaxial layer of the MN compound on the seed crystal.
    Type: Application
    Filed: March 4, 2012
    Publication date: December 19, 2013
    Applicant: Mosiac Crystals Ltd.
    Inventor: Moshe Einav
  • Patent number: RE45238
    Abstract: A silicon wafer in which both occurrences of slip dislocation and warpage are suppressed in device manufacturing processes is a silicon wafer having BMDs having an octahedral shape, wherein BMDs located at a position below the silicon wafer surface to a depth of 20 ?m and having a diagonal length of 200 nm or more are present at a concentration of ?2×109/cm3, and BMDs located at a position below a depth ?50 ?m have a diagonal length of ?10 nm to ?50 nm and a concentration of ?1×1012/cm3.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: November 11, 2014
    Assignee: Siltronic AG
    Inventors: Masayuki Fukuda, Katsuhiko Nakai