With Pretreatment Or Preparation Of A Base (e.g., Annealing) Patents (Class 117/106)
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Patent number: 8608849Abstract: A method for making zinc oxide nano-structure, the method includes the following steps. Firstly, providing a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, providing a growing substrate and forming a metal layer thereon. Thirdly, depositing a catalyst layer on the metal layer. Fourthly, placing the growing substrate into the reacting room together with a quantity of zinc source material. Fifthly, introducing a oxygen-containing gas into the reacting room. Lastly, heating the reacting room to a temperature range of 500˜1100° C.Type: GrantFiled: September 29, 2008Date of Patent: December 17, 2013Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Hai-Lin Sun, Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
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Publication number: 20130313686Abstract: A method for manufacturing a semiconductor device includes: (a) providing a base unit made of a material having a first lattice constant; (b) forming a first sacrificial layer made of a material having a second lattice constant on the base unit and a second sacrificial layer made of a material having a third lattice constant on the first sacrificial layer, the first lattice constant ranging between the second and third lattice constants so that two lattice stresses in opposite directions occur in the epitaxial substrate; (c) forming an epitaxial unit on the second sacrificial layer; (d) forming a permanent substrate on the epitaxial unit; and (e) removing the epitaxial unit.Type: ApplicationFiled: March 18, 2013Publication date: November 28, 2013Applicant: NATIONAL CHUNG-HSING UNIVERSITYInventors: Ray-Hua Horng, Ming-Chun Tseng, Fan-Lei Wu
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Patent number: 8551246Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.Type: GrantFiled: May 7, 2009Date of Patent: October 8, 2013Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
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Patent number: 8551363Abstract: A method of producing a Group II-VI compound semiconductor. The method involves generating a pulsed electrical discharge plasma between metallic electrodes in sulfur to produce a Group II-VI compound semiconductor. A method of producing a Group II-VI compound semiconductor phosphor using a pulsed electrical discharge plasma. A hexagonal crystal of Group II-VI compound semiconductor composed of a plurality of twin crystals.Type: GrantFiled: February 5, 2009Date of Patent: October 8, 2013Assignees: National University Corporation Kumamoto University, Kuraray Co., Ltd.Inventors: Tsutomu Mashimo, Omurzak Uulu Emil, Makoto Okamoto, Hideharu Iwasaki
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Publication number: 20130255566Abstract: A method for making an epitaxial structure includes the following steps. A substrate having an epitaxial growth surface is provided. A buffer layer is formed on the epitaxial growth surface. A carbon nanotube layer is placed on the buffer layer. A first epitaxial layer is epitaxially grown on the buffer layer. The substrate and the buffer layer are removed to expose a second epitaxial growth surface. A second epitaxial layer is epitaxially grown on the second epitaxial growth surface.Type: ApplicationFiled: August 24, 2012Publication date: October 3, 2013Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITYInventors: YANG WEI, SHOU-SHAN FAN
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Publication number: 20130255568Abstract: A method for manufacturing silicon carbide single crystal having a diameter larger than 100 mm by sublimation includes the following steps. A seed substrate made of silicon carbide and silicon carbide raw material are prepared. Silicon carbide single crystal is grown on the growth face of the seed substrate by sublimating the silicon carbide raw material. In the step of growing silicon carbide single crystal, the maximum growing rate of the silicon carbide single crystal growing on the growth face of the seed substrate is greater than the maximum growing rate of the silicon carbide crystal growing on the surface of the silicon carbide raw material. Thus, there can be provided a method for manufacturing silicon carbide single crystal allowing a thick silicon carbide single crystal film to be obtained, when silicon carbide single crystal having a diameter larger than 100 mm is grown.Type: ApplicationFiled: February 28, 2013Publication date: October 3, 2013Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hiroki INOUE, Makoto SASAKI, Shin HARADA, Eiryo TAKASUKA, Shinsuke FUJIWARA
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Publication number: 20130255565Abstract: A method for making an epitaxial structure includes the following steps. A substrate having an epitaxial growth surface is provided. A buffer layer is formed on the epitaxial growth surface. A carbon nanotube layer is placed on the buffer layer. A first epitaxial layer is epitaxially grown on the buffer layer. The substrate and the buffer layer are removed to expose a second epitaxial growth surface. A second epitaxial layer is epitaxially grown on the second epitaxial growth surface.Type: ApplicationFiled: August 24, 2012Publication date: October 3, 2013Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITYInventors: YANG WEI, SHOU-SHAN FAN
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Publication number: 20130255567Abstract: A method for making an epitaxial base includes the following steps. A plurality of grooves and a plurality of bulges are formed on an epitaxial growth surface of a substrate by etching the epitaxial growth surface. A carbon nanotube layer is located on the epitaxial growth surface, wherein the carbon nanotube layer defines a first part attached on top surface of bulges, and a second part suspended on the grooves. The second part of the carbon nanotube layer is attached on bottom surface of the grooves by treating the carbon nanotube layer.Type: ApplicationFiled: October 9, 2012Publication date: October 3, 2013Inventors: YANG WEI, SHOU-SHAN FAN
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Publication number: 20130240876Abstract: The present invention relates to a method for growing a novel non-polar (13 40) plane epitaxy layer of wurtzite structure, which comprises the following steps: providing a single crystal oxide with perovskite structure; using a plane of the single crystal oxide as a substrate; and forming a non-polar (13 40) plane epitaxy layer of wurtzite semiconductors on the plane of the single crystal oxide by a vapor deposition process. The present invention also provides an epitaxy layer having non-polar (13 40) plane obtained according to the aforementioned method.Type: ApplicationFiled: March 13, 2013Publication date: September 19, 2013Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Li CHANG, Yen-Teng HO
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Publication number: 20130239881Abstract: A method for manufacturing a silicon carbide single-crystal having a diameter of more than 100 mm and a maximum height of 20 mm or more using a sublimation method includes the following steps. That is, there are prepared a seed substrate made of silicon carbide and a silicon carbide source material. By sublimating the silicon carbide source material, the silicon carbide single-crystal is grown on a growth surface of the seed substrate. In the step of growing the silicon carbide single-crystal, a first carbon member provided at a position facing a side wall of the seed substrate is etched at a rate of 0.1 mm/hour or less. By suppressing a change in growth condition for the silicon carbide single-crystal in the crucible, there can be provided a method for manufacturing a silicon carbide single-crystal so as to stably grow the silicon carbide single-crystal.Type: ApplicationFiled: January 30, 2013Publication date: September 19, 2013Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hiroki INOUE, Makoto SASAKI, Shin HARADA, Shinsuke FUJIWARA
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Publication number: 20130239879Abstract: A load lock includes a chamber including an upper portion, a lower portion, and a partition between the upper portion and the lower portion, the partition including an opening therethrough. The load lock further includes a first port in communication with the upper portion of the chamber and a second port in communication with the lower portion of the chamber. The load lock includes a rack disposed within the chamber and a workpiece holder mounted on a first surface of the rack, wherein the rack and the workpiece holder are movable by an indexer that is capable of selectively moving wafer slots of the rack into communication with the second port. The indexer can also move the rack into an uppermost position, at which the first surface of the boat and the partition sealingly separate the upper portion and the lower portion to define an upper chamber and a lower chamber. Auxiliary processing, such as wafer pre-cleaning, or metrology can be conducted in the upper portion.Type: ApplicationFiled: May 8, 2013Publication date: September 19, 2013Applicant: ASM AMERICA, INC.Inventors: Ravinder K. Aggarwal, Jeroen Stoutjesdijk, Eric R. Hill, Loring G. Davis, John T. DiSanto
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Publication number: 20130233238Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.Type: ApplicationFiled: February 15, 2013Publication date: September 12, 2013Applicant: IMECInventors: Benjamin Vincent, Aaron Thean, Liesbeth Witters
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Patent number: 8529699Abstract: A method includes the steps of, using water vapor and a metalorganic compound not containing oxygen, (a) performing crystal growth at a low growth temperature and at a low growth pressure in the range of 1 kPa to 30 kPa to form a low-temperature grown single-crystal layer; and (b) performing crystal growth at a high growth temperature and at a pressure higher than the low growth pressure to form a high-temperature grown single-crystal layer on the low-temperature grown single-crystal layer.Type: GrantFiled: September 16, 2009Date of Patent: September 10, 2013Assignee: Stanley Electric Co., Ltd.Inventors: Naochika Horio, Masayuki Makishima
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Patent number: 8529698Abstract: Methods, devices, and compositions of matter related to high efficiency InGaN-based photovoltaic devices. The disclosed synthesis of semiconductor heterostructures may be exploited to produce higher efficiency, longer lasting, photovoltaic cells.Type: GrantFiled: November 11, 2009Date of Patent: September 10, 2013Assignee: Arizona Board Of Regents For And On Behalf Of Arizona State UniversityInventors: Fernando A. Ponce, Rafael Garcia
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Publication number: 20130182249Abstract: Provided are patterned nanoporous gold (“P-NPG”) films that may act as at least one of an effective and stable surface-enhanced Raman scattering (“SERS”) substrate. Methods of fabricating the P-NPG films using a low-cost stamping technique are also provided. The P-NPG films may provide uniform SERS signal intensity and SERS signal intensity enhancement by a factor of at least about 1×107 relative to the SERS signal intensity from a non-enhancing surface.Type: ApplicationFiled: September 20, 2011Publication date: July 18, 2013Applicant: Vanderbilt UniversityInventors: Sharon M. Weiss, Yang Jiao, Judson D. Ryckman, Peter N. Ciesielski, G. Kane Jennings
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Publication number: 20130171402Abstract: A method is used for producing an SiC volume monocrystal by sublimation growth. Before the beginning of growth, an SiC seed crystal is arranged in a crystal growth region of a growth crucible and powdery SiC source material is introduced into an SiC storage region of the growth crucible. During the growth, by sublimation of the powdery SiC source material and by transport of the sublimated gaseous components into the crystal growth region, an SiC growth gas phase is produced there. The SiC volume monocrystal having a central center longitudinal axis grows by deposition from the SiC growth gas phase on the SiC seed crystal. The SiC seed crystal is heated substantially without bending during a heating phase before the beginning of growth, so that an SiC crystal structure with a substantially homogeneous course of lattice planes is provided in the SiC seed crystal.Type: ApplicationFiled: December 28, 2011Publication date: July 4, 2013Applicant: SiCRYSTAL AGInventors: THOMAS STRAUBINGER, MICHAEL VOGEL, ANDREAS WOHLFART
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Publication number: 20130171403Abstract: A method is used for producing an SiC volume monocrystal by sublimation growth. During growth, by sublimation of a powdery SiC source material and by transport of the sublimated gaseous components into the crystal growth region, an SiC growth gas phase is produced there. The SiC volume monocrystal grows by deposition from the SiC growth gas phase on the SiC seed crystal. The SiC seed crystal is bent during a heating phase before such that an SiC crystal structure with a non-homogeneous course of lattice planes is adjusted, the lattice planes at each point have an angle of inclination relative to the direction of the center longitudinal axis and peripheral angles of inclination at a radial edge of the SiC seed crystal differ in terms of amount by at least 0.05° and at most by 0.2° from a central angle of inclination at the site of the center longitudinal axis.Type: ApplicationFiled: December 28, 2011Publication date: July 4, 2013Applicant: SiCRYSTAL AGInventors: THOMAS STRAUBINGER, MICHAEL VOGEL, ANDREAS WOHLFART
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Publication number: 20130160699Abstract: Provided is a method of manufacturing III-nitride crystal having a major surface of plane orientation other than {0001}, designated by choice, the III-nitride crystal manufacturing method including: a step of slicing III-nitride bulk crystal through a plurality of planes defining a predetermined slice thickness in the direction of the designated plane orientation, to produce a plurality of III-nitride crystal substrates having a major surface of the designated plane orientation; a step of disposing the substrates adjoining each other sideways in a manner such that the major surfaces of the substrates parallel each other and such that any difference in slice thickness between two adjoining III-nitride crystal substrates is not greater than 0.1 mm; and a step of growing III-nitride crystal onto the major surfaces of the substrates.Type: ApplicationFiled: February 8, 2013Publication date: June 27, 2013Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Sumitomo Electric Industries, Ltd.
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Publication number: 20130145984Abstract: This invention relates to a method of epitaxial growth effectively preventing auto-doping effect. This method starts with the removal of impurities from the semiconductor substrate having heavily-doped buried layer region and from the inner wall of reaction chamber to be used. Then the semiconductor substrate is loaded in the cleaned reaction chamber to be pre-baked under vacuum conditions so as to remove moisture and oxide from the surface of said semiconductor substrate before the extraction of the dopant atoms desorbed from the surface of the semiconductor substrate. Next, under high temperature and low gas flow conditions, a first intrinsic epitaxial layer is formed on the surface of said semiconductor substrate where the dopant atoms have been extracted out. Following this, under low temperature and high gas flow conditions, a second epitaxial layer of required thickness is formed on the structural surface of the grown intrinsic epitaxial layer. Last, silicon wafer is unloaded after cooling.Type: ApplicationFiled: June 27, 2011Publication date: June 13, 2013Inventors: Chao Zhang, Zhitang Song, Xudong Wan, Bo Liu, Guanping Wu, Ting Zhang, Zuoya Yang
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Publication number: 20130149528Abstract: Some aspects of the invention provide an oxide substrate having a flat surface at the atomic layer level, and suited to forming a thin film of a perovskite manganese oxide. One aspect of the invention provides a single-crystal oxide substrate 10 having a single-crystal supporting substrate 1 of (210)-oriented SrTiO3 and a single-crystal underlayer 2 of (LaAlO3)0.3—(SrAl0.5Ta0.5O3)0.7, which is LSAT, formed on the (210) plane surface of the supporting substrate. In another aspect of the present invention, the LSAT underlayer 2A is formed in an amorphous state. Other aspects of the invention are also disclosed.Type: ApplicationFiled: February 12, 2013Publication date: June 13, 2013Applicant: FUJI ELECTRIC CO., LTD.Inventor: FUJI ELECTRIC CO., LTD.
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Patent number: 8430959Abstract: Disclosed are a method and an apparatus for preparing a polycrystalline silicon rod using a mixed core means, comprising: installing a first core means made of a resistive material together with a second core means made of silicon material in an inner space of a deposition reactor; electrically heating the first core means and pre-heating the second core by the first core means which is electrically heated; electrically heating the preheated second core means; and supplying a reaction gas into the inner space in a state where the first core means and the second core means are electrically heated for silicon deposition.Type: GrantFiled: May 11, 2007Date of Patent: April 30, 2013Assignee: Korea Research Institute of Chemical TechnologyInventors: Hee Young Kim, Kyung Koo Yoon, Yong Ki Park, Won Choon Choi, Won Wook So
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Publication number: 20130095294Abstract: A silicon carbide ingot excellent in uniformity in characteristics and a silicon carbide substrate obtained by slicing the silicon carbide ingot, and a method of manufacturing the same are obtained. A method of manufacturing a silicon carbide ingot includes the steps of preparing a base substrate having an off angle with respect to a (0001) plane not greater than 1° and composed of single crystal silicon carbide and growing a silicon carbide layer on a surface of the base substrate. In the step of growing a silicon carbide layer, a temperature gradient in a direction of width when viewed in a direction of growth of the silicon carbide layer is set to 10° C./cm or less.Type: ApplicationFiled: October 17, 2012Publication date: April 18, 2013Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: SUMITOMO ELECTRIC INDUSTRIES, LTD.
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Publication number: 20130095285Abstract: A silicon carbide substrate and a silicon carbide ingot excellent in uniformity in characteristics, and a method of manufacturing the same are obtained. A method of manufacturing a silicon carbide ingot includes the steps of preparing a base substrate having an off angle with respect to a (0001) plane not greater than 10° and composed of single crystal silicon carbide and growing a silicon carbide layer on a surface of the base substrate. In the step of growing a silicon carbide layer, a temperature gradient in a direction of width when viewed in a direction of growth of the silicon carbide layer is set to 20° C./cm or more.Type: ApplicationFiled: October 15, 2012Publication date: April 18, 2013Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: SUMITOMO ELECTRIC INDUSTRIES, LTD.
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Patent number: 8415546Abstract: Disclosed is a fabrication method of a metal nanoplate using metal, metal halide or a mixture thereof as a precursor. The single crystalline metal nanoplate is fabricated on a single crystalline substrate by performing heat treatment on a precursor including metal, metal halide or a mixture thereof and placed at a front portion of a reactor and the single crystalline substrate placed at a rear portion of the reactor under an inert gas flowing condition. A noble metal nanoplate of several micrometers in size can be fabricated using a vapor-phase transport process without any catalyst. The fabricated nanoplate is a single crystalline metal nanoplate having high crystallinity, high purity and not having a two-dimensional defect. Morphology and orientation of the metal nanoplate with respect to the substrate can be controlled by controlling a surface direction of the single crystalline substrate. The metal nanoplate of several micrometer size is mass-producible.Type: GrantFiled: September 22, 2009Date of Patent: April 9, 2013Assignee: Korea Advanced Institute of Science and TechnologyInventors: Bongsoo Kim, Youngdong Yoo
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Patent number: 8409349Abstract: A film thickness measurement method for measuring a change in film thickness of 0.3 ?m or less in a silicon wafer by FTIR, having an auxiliary film formation step for depositing an auxiliary film for measurement on a surface to be measured for the change in film thickness, an auxiliary film thickness measurement step for measuring the film thickness of the auxiliary film, a measurement step for measuring the film thickness of the auxiliary film after the change in film thickness, and a calculation step for calculating a change in film thickness of a back surface deposit from the result of the measurement step and the result of the auxiliary film thickness measurement step.Type: GrantFiled: June 9, 2009Date of Patent: April 2, 2013Assignee: Sumco CorporationInventor: Kazuhiro Ohkubo
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Patent number: 8409366Abstract: In a separation method of a nitride semiconductor layer, a graphene layer in the form of a single layer or two or more layers is formed on a surface of a first substrate. A nitride semiconductor layer is formed on the graphene layer so that the nitride semiconductor layer is bonded to the graphene layer with a bonding force due to regularity of potential at atomic level at an interface therebetween without utilizing covalent bonding. The nitride semiconductor layer is separated from the first substrate with a force which is greater than the bonding force between the nitride semiconductor layer and the graphene layer, or greater than a bonding force between respective layers of the graphene layer.Type: GrantFiled: June 22, 2010Date of Patent: April 2, 2013Assignee: Oki Data CorporationInventors: Mitsuhiko Ogihara, Tomohiko Sagimori, Masaaki Sakuta, Akihiro Hashimoto
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Patent number: 8404571Abstract: Provided is a film deposition method capable of improving the crystal characteristic near an interface according to the lattice constant of a material that will constitute a thin film to be deposited. Specifically, a substrate is curved relative to the direction along one main surface on which the thin film is to be deposited, according to the lattice constant the material that will constitute the thin film to be deposited and the lattice constant of a material constituting the one main surface. The thin film is deposited on the one main surface of the substrate with the substrate curved.Type: GrantFiled: June 25, 2009Date of Patent: March 26, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Hashimoto, Tatsuya Tanabe
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Publication number: 20130071643Abstract: A silicon carbide substrate capable of stably forming a device of excellent performance, and a method of manufacturing the same are provided. A silicon carbide substrate is made of a single crystal of silicon carbide, and has a width of not less than 100 mm, a micropipe density of not more than 7 cm?2, a threading screw dislocation density of not more than 1×104 cm?2, a threading edge dislocation density of not more than 1×104 cm?2, a basal plane dislocation density of not more than 1×104 cm?2, a stacking fault density of not more than 0.1 cm?1, a conductive impurity concentration of not less than 1×1018 cm?2, a residual impurity concentration of not more than 1×1016 cm?2, and a secondary phase inclusion density of not more than 1 cm?3.Type: ApplicationFiled: September 6, 2012Publication date: March 21, 2013Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shin HARADA, Shinsuke FUJIWARA, Taro NISHIGUCHI
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Patent number: 8394197Abstract: Enhanced corrosion resistance is achieved in a coating by using a germanium-containing precursor and hollow cathode techniques to form a first layer directly on the surface of a workpiece, prior to forming an outer layer, such as a layer of diamond-like carbon (DLC). The use of a germanium or germanium-carbide precursor reduces film stress and enables an increase in the thickness of the subsequently formed DLC. Germanium incorporation also reduces the porosity of the layer. In one embodiment, a cap layer containing germanium is added after the DLC in order to further reduce the susceptibility of the coating to chemical penetration from the top.Type: GrantFiled: July 11, 2008Date of Patent: March 12, 2013Assignee: Sub-One Technology, Inc.Inventors: Andrew W. Tudhope, Thomas B. Casserly, Karthik Boinapally, Deepak Upadhyaya, William J. Boardman
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Publication number: 20130052421Abstract: A method for fabricating a nanostructure utilizes a templated monocrystalline substrate. The templated monocrystalline substrate is energetically (i.e., preferably thermally) treated, with an optional precleaning and an optional amorphous material layer located thereupon, to form a template structured monocrystalline substrate that includes the monocrystalline substrate with a plurality of epitaxially aligned contiguous monocrystalline pillars extending therefrom. The monocrystalline substrate and the plurality of epitaxially aligned contiguous monocrystalline pillars may comprise the same or different monocrystalline materials.Type: ApplicationFiled: March 4, 2011Publication date: February 28, 2013Applicant: Cornell University- Cornell Center for TechnologyInventors: Ulrich Wiesner, Michael Thompson, Hitesh Arora
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Patent number: 8382894Abstract: Silicon wafers wherein slip dislocations and warpages during device production are suppressed, contain BMDs with an octahedral shape, and of BMDs at a depth greater than 50 ?m from the surface of the wafer, the density of BMDs with diagonal size of 10 nm to 50 nm is ?1×1012/cm3, and the density of BSFs is ?1×108/cm3. The present silicon wafers preferably have an interstitial oxygen concentration of 4×1017 atoms/cm3 to 6×1017 atoms/cm3, and a density of BMDs with diagonal size of ?200 nm of not more than 1×107/cm3.Type: GrantFiled: October 26, 2009Date of Patent: February 26, 2013Assignee: Siltronic AGInventors: Katsuhiko Nakai, Masayuki Fukuda
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Publication number: 20130042801Abstract: Embodiments described herein provide processes for forming and removing epitaxial films and materials from growth wafers by epitaxial lift off (ELO) processes. In some embodiments, the growth wafer has edge surfaces with an off-axis orientation which is utilized during the ELO process. The off-axis orientation of the edge surface provides an additional variable for controlling the etch rate during the ELO process- and therefore the etch front may be modulated to prevent the formation of high stress points which reduces or prevents stressing and cracking the epitaxial film stack. In one embodiment, the growth wafer is rectangular and has an edge surface with an off-axis orientation rotated by an angle greater than 0° and up to 90° relative to an edge orientation of <110> at 0°.Type: ApplicationFiled: August 15, 2011Publication date: February 21, 2013Inventors: Thomas Gmitter, Gang He, Melissa Archer, Siew Neo
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Patent number: 8349076Abstract: A method of fabricating a freestanding gallium nitride (GaN) substrate includes: preparing a GaN substrate within a reactor; supplying HCl and NH3 gases into the reactor to treat the surface of the GaN substrate and forming a porous GaN layer; forming a GaN crystal growth layer on the porous GaN layer; and cooling the GaN substrate on which the GaN crystal growth layer has been formed and separating the GaN crystal growth layer from the substrate. According to the fabrication method, the entire process including forming a porous GaN layer and a thick GaN layer is performed in-situ within a single reactor. The method is significantly simplified compared to a conventional fabrication method. The fabrication method enables the entire process to be performed in one chamber while allowing GaN surface treatment and growth to be performed using HVPE process gases, thus resulting in a significant reduction in manufacturing costs.Type: GrantFiled: October 11, 2006Date of Patent: January 8, 2013Assignee: Samsung Corning Precision Materials Co., Ltd.Inventors: In-Jae Song, Jai-yong Han
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Publication number: 20130000547Abstract: The object of the present invention is to provide a method for fixing a silicon carbide seed crystal and a method for producing a silicon carbide single crystal which can produce a silicon carbide single crystal having high quality and no penetration defects, and the present invention provides a method for fixing a silicon carbide seed crystal on a pedestal including: a step of mirror polishing a surface of a pedestal on which a silicon carbide seed crystal is to be fixed; a step of irradiating atoms or ions to at least one of a seed crystal-side surface of the pedestal on which the silicon carbide seed crystal is to be fixed and a pedestal side-surface of the silicon carbide seed crystal which is to be fixed on the pedestal, in a vacuum; and a step of directly connecting the seed crystal side-surface of the pedestal and the pedestal side-surface of the silicon carbide seed crystal by bringing them into close contact and applying pressure to them in a vacuum.Type: ApplicationFiled: March 2, 2011Publication date: January 3, 2013Applicant: SHOWA DENKO K.K.Inventor: Hisao Kogoi
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Patent number: 8343618Abstract: A silicon wafer in which both occurrences of slip dislocation and warpage are suppressed in device manufacturing processes is a silicon wafer having BMDs having an octahedral shape, wherein BMDs located at a position below the silicon wafer surface to a depth of 20 ?m and having a diagonal length of 200 nm or more are present at a concentration of ?2×109/cm3, and BMDs located at a position below a depth ?50 ?m have a diagonal length of ?10 nm to ?50 nm and a concentration of ?1×1012/cm3.Type: GrantFiled: December 15, 2009Date of Patent: January 1, 2013Assignee: Siltronic AGInventors: Masayuki Fukuda, Katsuhiko Nakai
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EPTAXIAL SUBSTRATE, METHOD FOR MAKING THE SAME AND METHOD FOR GROWING EPITAXIAL LAYER USING THE SAME
Publication number: 20120325139Abstract: An epitaxial substrate is provided, the epitaxial substrate is used to grow epitaxial layer. The epitaxial substrate includes a base having a number of grooves to form a patterned epitaxial growth surface. The patterned epitaxial growth surface is referred as an epitaxial growth surface. A carbon nanotube layer covers on the epitaxial growth surface, and the carbon nanotube layer corresponding to the grooves is suspended on the epitaxial substrate.Type: ApplicationFiled: December 23, 2011Publication date: December 27, 2012Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITYInventors: YANG WEI, SHOU-SHAN FAN -
Patent number: 8328936Abstract: A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.Type: GrantFiled: October 18, 2011Date of Patent: December 11, 2012Assignee: Nippon Telegraph and Telephone CorporationInventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
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Publication number: 20120305983Abstract: The method for producing a group III nitride semiconductor crystal comprises preparing a seed crystal having a non-polar plane followed by growing a group III nitride semiconductor from the non-polar plane in a vapor phase, wherein the growing includes growing the group III nitride semiconductor so as to extend in the +C-axis direction of the seed crystal. A group III-V nitride semiconductor crystal having high quality and a large-area non-polar plane can be obtained by the method.Type: ApplicationFiled: August 10, 2012Publication date: December 6, 2012Applicant: MITSUBISHI CHEMICAL CORPORATIONInventors: Kenji Fujito, Kazumasa Kiyomi
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Publication number: 20120304918Abstract: A method of growing a p-type thin film of ?-Ga2O3 includes preparing a substrate including a ?-Ga2O3 single crystal, and growing a p-type thin film of ?-Ga2O3 on the substrate. The p-type thin film is grown in a manner that Ga in the thin film is replaced by a p-type dopant selected from H, Li, Na, K, Rb, Cs, Fr, Be, Mg, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Tl, and Pb.Type: ApplicationFiled: August 13, 2012Publication date: December 6, 2012Inventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
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Publication number: 20120304919Abstract: A method for growing germanium epitaxial films is disclosed. Initially, a silicon substrate is preconditioned with hydrogen gas. The temperature of the preconditioned silicon substrate is then decreased, and germane gas is flowed over the preconditioned silicon substrate to form an intrinsic germanium seed layer. Next, a mixture of germane and phosphine gases can be flowed over the intrinsic germanium, seed layer to produce an n-doped germanium seed layer. Otherwise, a mixture of diborane and germane gases can be flowed over the intrinsic germanium seed layer to produce a p-doped germanium seed layer. At this point, a hulk germanium layer can be grown on top of the doped germanium seed layer.Type: ApplicationFiled: August 15, 2012Publication date: December 6, 2012Applicant: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Daniel N. Carothers, Craig M. Hill, Andrew T.S. Pomerene, Vu A. Vu
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Patent number: 8323402Abstract: Methods of growing and manufacturing aluminum nitride crystal, and aluminum nitride crystal produced by the methods. Preventing sublimation of the starting substrate allows aluminum nitride crystal of excellent crystallinity to be grown at improved growth rates. The aluminum nitride crystal growth method includes the following steps. Initially, a laminar baseplate is prepared, furnished with a starting substrate having a major surface and a back side, a first layer formed on the back side, and a second layer formed on the first layer. Aluminum nitride crystal is then grown onto the major surface of the starting substrate by vapor deposition. The first layer is made of a substance that at the temperatures at which the aluminum nitride crystal is grown is less liable to sublimate than the starting substrate. The second layer is made of a substance whose thermal conductivity is higher than that of the first layer.Type: GrantFiled: December 19, 2008Date of Patent: December 4, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keisuke Tanizaki, Naho Mizuhara, Michimasa Miyanaga, Hideaki Nakahata, Yoshiyuki Yamamoto
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Publication number: 20120294790Abstract: A method of manufacturing a silicon carbide ingot having highly uniform characteristics includes a preparation step of preparing a base substrate made of single crystal silicon carbide and having an off angle of 0.1° or more and 10° or less in an off angle direction which is either a <11-20> direction or a <1-100> direction relative to a (0001) plane, and a film formation step of growing a silicon carbide layer on a surface of the base substrate. In the film formation step, a region having a (0001) facet 5 is formed on a surface of the grown silicon carbide layer at an end portion on an upstream side, the upstream side being a side where an angle of intersection between a <0001> direction axis of the base substrate and the surface of the base substrate in the off angle direction is an acute angle.Type: ApplicationFiled: May 16, 2012Publication date: November 22, 2012Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Makoto SASAKI, Taro Nishiguchi
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Publication number: 20120275984Abstract: Each of first and second material substrates made of single crystal silicon carbide has first and second back surfaces, first and second side surfaces, and first and second front surfaces. The first and second back surfaces are connected to a supporting portion. The first and second side surfaces face each other with a gap interposed therebetween, the gap having an opening between the first and second front surfaces. A closing portion for closing the gap over the opening is formed. A connecting portion for closing the opening is formed by depositing a sublimate from the first and second side surfaces onto the closing portion. The closing portion is removed. A silicon carbide single crystal is grown on the first and second front surfaces.Type: ApplicationFiled: February 25, 2011Publication date: November 1, 2012Applicant: Sumitomo Electric Industries, Ltd.Inventors: Taro Nishiguchi, Shin Harada, Makoto Sasaki
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Publication number: 20120267606Abstract: A group III nitride crystal substrate is provided, wherein, a uniform distortion at a surface layer of the crystal substrate is equal to or lower than 1.7×10?3, and wherein a plane orientation of the main surface has an inclination angle equal to or greater than ?10° and equal to or smaller than 10° in a [0001] direction with respect to a plane including a c axis of the crystal substrate. A group III nitride crystal substrate suitable for manufacturing a light emitting device with a blue shift of an emission suppressed, an epilayer-containing group III nitride crystal substrate, a semiconductor device and a method of manufacturing the same can thereby be provided.Type: ApplicationFiled: June 18, 2012Publication date: October 25, 2012Inventors: Keiji ISHIBASHI, Yusuke Yoshizumi, Shugo Minobe
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Publication number: 20120241821Abstract: A heterostructure that includes, successively, a support substrate of a material having an electrical resistivity of less than 10?3 ohm·cm and a thermal conductivity of greater than 100 W·m?1·K?1, a bonding layer, a first seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, a second seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and an active layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and being present in a thickness of between 3 and 100 micrometers. The materials of the support substrate, the bonding layer and the first seed layer are refractory at a temperature of greater than 750° C., the active layer and second seed layer have a difference in lattice parameter of less than 0.005 ?, the active layer is crack-free, and the heterostructure has a specific contact resistance between the bonding layer and the first seed layer that is less than or equal to 0.1 ohm·cm2.Type: ApplicationFiled: December 1, 2010Publication date: September 27, 2012Applicant: SOITECInventors: Jean-Marc Bethoux, Fabrice Letertre, Chris Werkhoven, Ionut Radu, Oleg Kononchuck
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Patent number: 8268076Abstract: SOI wafers are manufactured by forming on a silicon substrate a monocrystalline first, cubic 1a-3 metal or mixed metal oxide layer whose lattice constant differs from that of the substrate by 5% or less; forming a second cubic 1a-3 mixed metal oxide layer having a lattice constant within 2% of the lattice constant of the first metal or mixed metal oxide layer, and having a graded metal content to vary the lattice content in the second mixed metal oxide layer from that of the first layer, and thermally treating the layered product in an oxygen atmosphere to form an amorphous interlayer between the substrate and the first metal or mixed metal oxide layer.Type: GrantFiled: May 13, 2010Date of Patent: September 18, 2012Assignee: Siltronic AGInventors: Thomas Schroeder, Peter Storck, Hans Joachim Muessig
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Patent number: 8263483Abstract: A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion.Type: GrantFiled: July 7, 2009Date of Patent: September 11, 2012Assignee: Infineon Technologies Austria AGInventors: Franz Hirler, Hans-Joachim Schulze
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Patent number: 8226767Abstract: “Super-hetero-epitaxial” combinations comprise epitaxial growth of one material on a different material with different crystal structure. Compatible crystal structures may be identified using a “Tri-Unity” system. New bandgap engineering diagrams are provided for each class of combination, based on determination of hybrid lattice constants for the constituent materials in accordance with lattice-matching equations. Using known bandgap figures for previously tested materials, new materials with lattice constants that match desired substrates and have the desired bandgap properties may be formulated by reference to the diagrams and lattice matching equations. In one embodiment, this analysis makes it possible to formulate new super-hetero-epitaxial semiconductor systems, such as systems based on group IV alloys on c-plane LaF3; group IV alloys on c-plane langasite; Group III-V alloys on c-plane langasite; and group II-VI alloys on c-plane sapphire.Type: GrantFiled: October 20, 2008Date of Patent: July 24, 2012Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Yeonjoon Park, Sang H. Choi, Glen C. King, James R. Elliott
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Publication number: 20120183767Abstract: A III-N on silicon structure including a substrate of single crystal silicon with a cubic crystal structure and a layer of single crystal III-N material. First and second single crystal transition layers are positioned in overlying relationship with the layers graduated from a cubic crystal structure at one surface to a hexagonal crystal structure at an opposed surface. The first and second transition layers are positioned between the substrate and the layer of III-N material with the one surface lattice matched to the substrate and the opposed surface lattice matched to the layer of III-N material.Type: ApplicationFiled: December 16, 2011Publication date: July 19, 2012Inventors: Rytis Dargis, Andrew Clark, Michael Lebby
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Patent number: 8221548Abstract: A process for producing a diamond thin-film includes forming a diamond crystal thin-film on a substrate and firing the diamond crystal thin-film at a sufficient temperature under high pressure under which a diamond is stable. A diamond single-crystal substrate having a diamond single-crystal thin-film formed thereon is placed in an ultra-high-pressure and high-temperature firing furnace to anneal the diamond single-crystal thin-film under the conditions of 1200° C. and 6 GPa.Type: GrantFiled: January 31, 2008Date of Patent: July 17, 2012Assignee: Nippon Telegraph and Telephone CorporationInventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi