Epitaxy Formation Patents (Class 117/9)
  • Patent number: 7452792
    Abstract: The invention relates to a method of forming a layer of elastically unstrained crystalline material intended for electronics, optics, or optronics applications, wherein the method is carried out using a structure that includes a first crystalline layer which is elastically strained under tension (or respectively in compression) and a second crystalline layer which is elastically strained in compression (or respectively under tension), with the second layer being adjacent to the first layer.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: November 18, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Nicolas Daval, Zohra Chahra, Romain Larderet
  • Patent number: 7438759
    Abstract: An ambient environment nanowire sensor and corresponding fabrication method have been provided. The method includes: forming a substrate such as Silicon (Si) or glass; growing nanowires; depositing an insulator layer overlying the nanowires; etching to expose tips of the nanowires; forming a patterned metal electrode, with edges, overlying the tips of the nanowires; and, etching to expose the nanowires underlying the electrode edges. The nanowires can be a material such as IrO2, TiO2, InO, ZnO, SnO2, Sb2O3, or In2O3, to mane just a few examples. The insulator layer can be a spin-on glass (SOG) or low-k dielectric. In one aspect, the resultant structure includes exposed nanowires grown from the doped substrate regions and an insulator core with embedded nanowires. In a different aspect, the method forms a growth promotion layer overlying the substrate. The resultant structure includes exposed nanowires grown from the selectively formed growth promotion layer.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: October 21, 2008
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Fengyan Zhang, Robert A. Barrowcliff, Jong-Jan Lee, Sheng Teng Hsu
  • Publication number: 20080237809
    Abstract: A method of fabricating a hybrid orientation substrate is described. A silicon substrate with a first orientation having a silicon layer with a second orientation directly thereon is provided, and then a stress layer is formed on the silicon layer. A trench is formed between a first portion and a second portion of the silicon layer through the stress layer and into the substrate. The first portion of the silicon layer is amorphized. A SPE process is performed to recrystallize the amorphized first portion of the silicon layer to be a recrystallized layer with the first orientation. An annealing process is performed at a temperature lower than 1200° C. to convert a surface layer of the second portion of the silicon layer to a strained layer. The trench is filled with an insulating material after the SPE process or the annealing process, and the stress layer is removed.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yao-Tsung Huang, Chien-Ting Lin, Che-Hua Hsu, Guang-Hwa Ma
  • Patent number: 7422630
    Abstract: Concentration of metal element which promotes crystallization of silicon and which exists within a crystal silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is implemented after introducing nickel to an amorphous silicon film 103. Then, laser light is irradiated to diffuse the nickel element concentrated locally. After that, another heat treatment is implemented within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. A thermal oxide film 106 is formed in this step. At this time, the nickel element is gettered to the thermal oxide film 106. Then, the thermal oxide film 106 is removed. Thereby, a crystal silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: September 9, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame
  • Patent number: 7413604
    Abstract: The present invention provides a process for producing a polycrystal silicon film which comprises a step of forming a polycrystal silicon film by light irradiation of a silicon film set on a substrate, and a step of selecting substrate samples having an average grain size in a plane of the sample of 500 nm or more. According to the present invention, stable production of a high-performance poly-silicon TFT liquid crystal display becomes possible.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: August 19, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Takeda, Masakazu Saito, Yukio Takasaki, Hironobu Abe, Makoto Ohkura, Yoshinobu Kimura, Takeo Shiba
  • Publication number: 20080178793
    Abstract: Techniques for the formation of a higher purity semiconductor ingot using a low purity semiconductor feedstock include associating within a crucible a low-grade silicon feedstock, which crucible forms a process environment of said molten silicon. The process associates with the low-grade silicon feedstock, a quantity of the at least one metal and includes forming within the crucible a molten solution (e.g., a binary or ternary solution) of molten silicon and the metal at a temperature below the melting temperature of said low-grade silicon feedstock. A silicon seed crystal associates with the molten solution within the crucible for inducing directional silicon crystallization. The process further forms a silicon ingot from a portion of the molten solution in association with the silicon seed. The silicon ingot includes at least one silicon crystalline formation grown in the induced directional silicon crystallization process.
    Type: Application
    Filed: January 31, 2007
    Publication date: July 31, 2008
    Inventors: Matthias Heuer, Fritz Kirscht, Dieter Linke, Jean Patrice Rakotoniana, Kamel Ounadjela
  • Patent number: 7387677
    Abstract: The substrate is used for opto-electric or electrical devices and comprises a layer of nitride grown by means of vapor phase epitaxy growth wherein both main surfaces of the nitride substrate are substantially consisting of non N-polar face and N-polar face respectively and the dislocation density of the substrate is 5×105/cm2 or less. Therefore, the template type substrate has a good dislocation density and a good value of FWHM of the X-ray rocking curve from (0002) plane less than 80, so that the resulting template type substrate is very useful for the epitaxy substrate from gaseous phase such as MOCVD, MBE and HVPE, resulting in possibility of making good opto-electric devices such as Laser Diode and large-output LED and good electric devices such as MOSFET.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: June 17, 2008
    Assignees: AMMONO Sp. z o.o., Nichia Corporation
    Inventors: Robert Dwilinski, Roman Doradzinski, Jerzy Garczynski, Leszek Sierzputowski, Yasuo Kanbara
  • Publication number: 20080072816
    Abstract: A method for forming a structure of a desired cross-section on a substrate is provided. The method provides a seed structure comprising at least one support layer on the substrate. The support layer has a geometric shape related to the desired cross-section of the structure and is diffusive to a precursor constituent. The method further includes growing the structure by supplying at least one precursor constituent on the substrate. The desired cross-section of the structure is defined by the geometric shape of at least one support layer.
    Type: Application
    Filed: September 26, 2006
    Publication date: March 27, 2008
    Inventors: Walter H. Riess, Heike E. Riel, Siegfried F. Karg, Heinz Schmid
  • Patent number: 7348226
    Abstract: A method (and resultant structure) of forming a semiconductor structure, includes processing an oxide to have a crystalline arrangement, and depositing an amorphous semiconductor layer on the oxide by one of evaporation and chemical vapor deposition (CVD).
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: March 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Nestor Alexander Bojarczuk, Jr., Matthew Warren Copel, Supratik Guha, Vijay Narayanan
  • Patent number: 7335255
    Abstract: The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes. In the present invention, an amorphous semiconductor film is formed on an insulating surface, a metal element for promoting crystallization is added to the amorphous semiconductor film, the amorphous semiconductor film is heated to form a crystallized semiconductor film, a continuous wave laser beam is irradiated to the crystallized semiconductor film, and an upper portion of the crystallized semiconductor film is removed.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: February 26, 2008
    Assignee: Semiconductor Energy Laboratory, Co., Ltd.
    Inventors: Shinji Maekawa, Hidekazu Miyairi
  • Patent number: 7335261
    Abstract: Disclosed are apparatus for forming a semiconductor film having an excellent crystallinity from a non-single crystal semiconducting layer formed on a base layer made of an insulating material. The apparatus includes a light source, a homogenizer for homogenizing an intensity distribution of the emitted light, an amplitude-modulation means for performing the amplitude-modulation such that the amplitude of the light, of which the intensity distribution is homogenized, is increased in the direction of the relative motion of the light to the base layer, an optional light projection optical system for projecting the amplitude-modulated light onto the surface of the non-single crystal semiconductor such that a predetermined irradiation energy can be obtained, a phase shifter for providing a low temperature point in the surface irradiated by the light, and a substrate stage to move the light relative to the substrate thereby enabling scanning in the X and Y axis.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: February 26, 2008
    Assignee: Kabushiki Kaisha Ekisho Sentan Gijutsu Kaihatsu Center
    Inventors: Masakiyo Matsumura, Mikihiko Nishitani, Yoshinobu Kimura, Masayuki Jyumonji, Yukio Taniguchi, Masato Hiramatsu, Fumiki Nakano
  • Patent number: 7318866
    Abstract: The present invention is directed to systems and methods for irradiating regions of a thin film sample(s) with laser beam pulses having different energy beam characteristics that are generated and delivered via different optical paths.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: January 15, 2008
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James Im
  • Patent number: 7311771
    Abstract: A crystallization apparatus according to the present invention includes a first irradiation system which irradiates a predetermined area on a glass substrate having an irradiation target, i.e., an a-Si thin film with light beams having a substantially homogeneous light intensity distribution, and a second irradiation system which irradiates the predetermined area with light beams having a light intensity distribution with an inverse peak pattern that a light intensity is increased toward the periphery from an area in which the light intensity is minimum.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: December 25, 2007
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Yukio Taniguchi, Masakiyo Matsumura
  • Patent number: 7309476
    Abstract: Novel diamondoid-based components that may be used in nanoscale construction are disclosed. Such components include rods, brackets, screws, gears, rotors, and impellers. Subassemblies (or subsystems) may comprise one or more diamondoid components. Exemplary subassemblies include atomic force microscope tips, molecular tachometers and signal waveform generators, and self-assembling cellular membrane pores and channels.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: December 18, 2007
    Assignee: Chevron U.S.A. Inc.
    Inventors: Robert M. Carlson, Jeremy E. Dahl, Shenggao Liu
  • Patent number: 7306670
    Abstract: In the case of the epitaxial growth according to the prior art, a number o strips often have to be produced in a plane in order to restore an area to be repaired. This leads to overlapping and misorientation of the crystalline structures. In the case of the method according to the invention, the strip is of such a width that no overlapping occurs, since the width is adapted to the contour of the area to be repaired.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: December 11, 2007
    Assignee: Siemens Aktiengesellschaft
    Inventors: Thomas Beck, Georg Bostanjoglo, Nigel-Philip Cox, Rolf Wilkenhöner
  • Patent number: 7250081
    Abstract: Methods for repair of single crystal superalloys by laser welding and products thereof have been disclosed. The laser welding process may be hand held or automated. Laser types include: CO2, Nd:YAG, diode and fiber lasers. Parameters for operating the laser process are disclosed. Filler materials, which may be either wire or powder superalloys are used to weld at least one portion of a single crystal superalloy substrate.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: July 31, 2007
    Assignee: Honeywell International, Inc.
    Inventors: Yiping Hu, William F. Hehmann, Murali Madhava
  • Patent number: 7217319
    Abstract: A crystallization apparatus includes an illumination system which illuminates a phase shifter having a phase shift portion, and irradiates a polycrystal semiconductor film or an amorphous semiconductor film with a light beam having a predetermined light intensity distribution in which a light intensity is minimum in a point area corresponding to the phase shift portion of the phase shifter, thereby forming a crystallized semiconductor film, the phase shifter has four or more even-numbered phase shift lines which intersect at a point constituting the phase shift portion. An area on one side and an area on the other side of each phase shift line have a phase difference of approximately 180 degrees.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: May 15, 2007
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Masakiyo Matsumura, Yukio Taniguchi
  • Patent number: 7208041
    Abstract: An effective, simple and low-cost a method for growing single crystals of perovskite oxideshaving primary and secondary abnormal grain growths according to temperature condition higher than a determined temperature or an atmosphere of heat treatment, involves a perovskite seed single crystal being adjoined to a polycrystal of perovskite oxides and heating the adjoined combination whereby the seed single crystal grows into the polycrystal at the interface therebetween repressing secondary abnormal grain growths inside the polycrystal. 1) The composition ratio of the polycrystal is controlled and/or the specific component(s) of the polycrystal is(are) added in an excess amount compared to the amount of the component(s) of the original composition of the polycrystal, 2) the heating is performed in the temperature range which is over primary abnormal grain growths completion temperature and below secondary abnormal grain growths activation temperature, whereby the seed single crystal grows continuously.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: April 24, 2007
    Assignee: Ceracomp Co., Ltd.
    Inventors: Ho-Yong Lee, Jong-Bong Lee, Tae-Moo Hur
  • Patent number: 7150788
    Abstract: A method of adjusting the in-plane lattice constant of a substrate and an in-plane lattice constant adjusted substrate are provided. A crystalline substrate (1) made of SrTiO3 is formed at a first preestablished temperature thereon with a first epitaxial thin film (2) made of a first material, e. g., BaTiO3, and then on the first epitaxial thin film (2) with a second epitaxial thin film (6) made of a second material, e. g., BaxSr1?xTiO3 (where 0<x<1), that contains a substance of the first material and another substance which together therewith is capable of forming a solid solution in a preestablished component ratio. Thereafter, the substrate is heat-treated at a second preselected temperature. Heat treated at the second preestablished temperature, the substrate has dislocations (4) introduced therein and the second epitaxial thin film (6) has its lattice constant relaxed to a value close to the lattice constant of bulk crystal of the second material.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: December 19, 2006
    Assignee: Japan Science and Technology Agency
    Inventors: Hideomi Koinuma, Masashi Kawasaki, Tomoteru Fukumura, Kota Terai
  • Patent number: 7105048
    Abstract: Each region, which should be left on a substrate after patterning, of a semiconductor film is grasped in accordance with a mask. Then, each region to be scanned with laser light is determined so that at least the region to be obtained through the patterning is crystallized, and a beam spot is made to hit the region to be scanned, thereby partially crystallizing the semiconductor film. Each portion with low output energy of the beam spot is shielded by a slit. In the present invention, the laser light is not scanned and irradiated onto the entire surface of the semiconductor film but is scanned such that at least each indispensable portion is crystallized to a minimum. With the construction described above, it becomes possible to save time taken to irradiate the laser light onto each portion to be removed through the patterning after the crystallization of the semiconductor film.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: September 12, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Masaaki Hiroki, Koichiro Tanaka, Aiko Shiga, Satoshi Murakami, Mai Akiba
  • Patent number: 7041580
    Abstract: A laser-annealing method includes the steps of a first step of cleaning a non-monocrystal silicon film formed on a substrate, and a second step of laser-annealing the non-monocrystal silicon film in an atmosphere containing oxygen therein, wherein the first and second steps are conducted continuously without being exposed to the air. Also, a laser-annealing device includes a cleaning chamber, and a laser irradiation chamber, wherein a substrate to be processed is transported between the cleaning chamber and the laser irradiation chamber without being exposed to the air.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: May 9, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoto Kusumoto, Toru Takayama, Masato Yonezawa
  • Patent number: 7025826
    Abstract: Methods for biaxially-texturing a surface-region of an amorphous material are disclosed, comprising depositing an amorphous material onto a substrate, and supplying active oxygen near the substrate during ion beam bombardment of the amorphous material to create an amorphous material having a biaxially textured surface, wherein the ion beam bombardment occurs at a predetermined oblique incident angle. Methods for producing high-temperature coated superconductors are also disclosed, comprising depositing an amorphous buffer film onto a metal alloy substrate, bombarding a surface-region of the amorphous buffer film with an ion beam at an oblique incident angle while supplying active oxygen to the surface-region of the amorphous buffer film in order to create a biaxially textured surface-region thereon, and growing a superconducting film on the biaxially textured surface-region of the amorphous buffer film to create a high-temperature coated superconductor.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: April 11, 2006
    Assignee: Superpower, Inc.
    Inventors: Venkat Selvamanickam, Xuming Xiong
  • Patent number: 7018874
    Abstract: A process for fabricating thin film transistors is disclosed, which comprises a two-step laser annealing process as follows: crystallizing the channel portion by irradiating the channel portion with an irradiation beam; and modifying the electric properties of the source and the drain by irradiating the source and the drain with an irradiation beam in a step independent to the first step of crystallizing the channel portion.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: March 28, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hongyong Zhang
  • Patent number: 7018468
    Abstract: A process of lateral crystallization is provided for increasing the lateral growth length (LGL). A localized region of the substrate is heated for a short period of time. While the localized region of the substrate is still heated, a silicon film overlying the substrate is irradiated to anneal the silicon film to crystallize a portion of the silicon film in thermal contact with the heated substrate region. A CO2 laser may be used as a heat source to heat the substrate, while a UV laser or a visible spectrum laser is used to irradiate and crystallize the film.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: March 28, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Apostolos T. Voutsas, Robert S. Sposili, Mark A. Crowder
  • Patent number: 6987037
    Abstract: One aspect of this disclosure relates to a method for forming a strained silicon over silicon germanium (Si/SiGe) structure. In various embodiments, germanium ions are implanted into a silicon substrate with a desired dose and energy to be located beneath a surface silicon layer in the substrate. The implantation of germanium ions at least partially amorphizes the surface silicon layer. The substrate is heat treated to regrow a crystalline silicon layer over a resulting silicon germanium layer using a solid phase epitaxial (SPE) process. The crystalline silicon layer is strained by a lattice mismatch between the silicon germanium layer and the crystalline silicon layer. Other aspects are provided herein.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: January 17, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 6969425
    Abstract: Layers of boron-doped silicon having reduced out-of-plane curvature are disclosed. The layers have substantially equal concentrations of boron near the top and bottom surfaces. Since the opposing concentrations are substantially equal, the compressive stresses on the layers are substantially balanced, thereby resulting in layers with reduced out-of-plane curvature.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: November 29, 2005
    Assignee: Honeywell International Inc.
    Inventors: Cleopatra Cabuz, Max C. Glenn, Francis M. Erdmann, Robert D. Horning
  • Patent number: 6902617
    Abstract: A method of single crystal welding is provided for the production of a single crystal region (1) on a surface (2) of a moncrystalline substrate (3) by means of an energy beam (4). The method of single crystal welding includes the supply of a coating material (5), the formation of a melt (6) by melting the coating material (5) by means of the energy beam (4) and the melting of a surface layer (71, 72) of the single crystal substrate (3) by the energy beam (4). The characteristic (8) of the energy distribution in the energy beam (4) is set, in this connection, such that the lateral thermal flow (H1) from the melt into the single crystal substrate (3) is minimized.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: June 7, 2005
    Assignee: Sulzer Markets and Technology AG
    Inventor: Jürgen Betz
  • Patent number: 6887311
    Abstract: There is provided a method of forming an ohmic electrode, including the steps of: forming a hafnium layer on a surface of an n type nitride-based compound semiconductor layer to have a thickness of 1 to 15 nm; forming an aluminum layer on the hafnium layer; and annealing the hafnium layer and the aluminum layer to form a layer formed of hafnium and aluminum mixed together.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: May 3, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Mayuko Fudeta, Toshio Hata
  • Patent number: 6830616
    Abstract: The nickel element is provided selectively, i.e., adjacent to part of the surface of an amorphous silicon film in a long and narrow opening. The amorphous silicon film is irradiated with linear infrared light beams emitted from respective linear infrared lamps while scanned with the linear beams perpendicularly to the longitudinal direction of the opening. The longitudinal direction of the linear beams are set coincident with that of the opening. The infrared light beams are absorbed by the silicon film mainly as thermal energy, whereby a negative temperature gradient is formed in the silicon film. The temperature gradient moves as the lamps are moved for the scanning. The direction of the negative temperature gradient is set coincident with the lamp movement direction and an intended crystal growth direction, which enables crystal growth to proceed parallel with a substrate uniformly over a long distance.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: December 14, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Patent number: 6818059
    Abstract: The present invention is related to a method of crystallizing an amorphous silicon layer and a crystallizing apparatus thereof which crystallize an amorphous silicon layer using plasma. The present invention includes the steps of depositing an inducing substance for silicon crystallization on an amorphous silicon layer by plasma exposure, and carrying out annealing on the amorphous silicon layer to the amorphous silicon layer. The present invention includes a chamber having an inner space, a substrate support in the chamber wherein the substrate support supports a substrate, a plasma generating means in the chamber wherein the plasma generating means produces plasma inside the chamber, and a heater at the substrate support wherein the heater supplies the substrate with heat.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: November 16, 2004
    Assignees: LG. Philips LCD Co., Ltd.
    Inventors: Jin Jang, Soo-Young Yoon, Jae-Young Oh, Woo-Sung Shon, Seong-Jin Park
  • Publication number: 20040221792
    Abstract: One aspect of this disclosure relates to a method for forming a strained silicon over silicon germanium (Si/SiGe) structure. In various embodiments, germanium ions are implanted into a silicon substrate with a desired dose and energy to be located beneath a surface silicon layer in the substrate. The implantation of germanium ions at least partially amorphizes the surface silicon layer. The substrate is heat treated to regrow a crystalline silicon layer over a resulting silicon germanium layer using a solid phase epitaxial (SPE) process. The crystalline silicon layer is strained by a lattice mismatch between the silicon germanium layer and the crystalline silicon layer. Other aspects are provided herein.
    Type: Application
    Filed: May 7, 2003
    Publication date: November 11, 2004
    Applicant: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 6802902
    Abstract: A process for producing an epitaxial layer of gallium nitride (GaN). A film of a dielectric whose thickness is about one monolayer is formed on a surface of a substrate. A continuous gallium nitride layer is then deposited on the dielectric film at a temperature sufficiently low to suppress island formation of the gallium nitride. The deposited gallium nitride layer is annealed at a temperature sufficiently high to promote island formation of the gallium nitride. An epitaxial regrowth with gallium nitride at the end of a spontaneous in situ formation of islands of gallium nitride then takes place. This method makes it possible to avoid having to use ex situ etching of masks by photolitographiy or chemical ethching techniques.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: October 12, 2004
    Assignee: Lumilog
    Inventors: Bernard Beaumont, Pierre Gibart, Jean-Claude Guillaume, Gilles Nataf, Michel Vaille, Soufien Haffouz
  • Patent number: 6773502
    Abstract: Methods of forming an electrically conductive line include providing a stress inducing material within or a compressive stress inducing layer operatively adjacent a crystalline material of a first crystalline phase. In addition, such methods include annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. Some methods also include providing stress inducing materials into a refractory metal layer. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials include Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: August 10, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Sujit Sharan
  • Patent number: 6743294
    Abstract: Reactive gas is released through a crystal source material or melt to react with impurities and carry the impurities away as gaseous products or as precipitates or in light or heavy form. The gaseous products are removed by vacuum and the heavy products fall to the bottom of the melt. Light products rise to the top of the melt. After purifying, dopants are added to the melt. The melt moves away from the heater and the crystal is formed. Subsequent heating zones re-melt and refine the crystal, and a dopant is added in a final heating zone. The crystal is divided, and divided portions of the crystal are re-heated for heat treating and annealing.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: June 1, 2004
    Assignee: Optoscint, Inc.
    Inventor: Kiril A. Pandelisev
  • Patent number: 6733584
    Abstract: To provide a method of promoting quality of crystals and increasing growth rate in a process of carrying out crystal growth in a horizontal direction of an amorphous silicon film by using a catalyst element expediting crystallization, in respect of the amorphous silicon film for carrying out horizontal growth by using a catalyst element of nickel or the like, irregularities of a matrix (underlayer film or substrate) in contact with the amorphous silicon film are made smaller than the film thickness of the amorphous silicon film by which crystal growth occurs substantially entirely by the catalyst element and interruption of growth caused by natural crystallization or the irregularities of a matrix can be prevented.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: May 11, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hisashi Ohtani
  • Patent number: 6677222
    Abstract: A first layer made of polysilicon is formed on the surface of an underlying substrate. The surface of the first layer is exposed to an environment which etches silicon oxide. If the surface of the first layer is covered with a silicon oxide film, the silicon oxide film is removed. An energy is supplied to the first layer, the energy allowing silicon crystal to re-grow. Solid phase growth of silicon occurs in the first layer to planarize the surface thereof. A polysilicon film having small root mean square of roughness can be formed.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: January 13, 2004
    Assignee: Fujitsu Limited
    Inventors: Yasuyoshi Mishima, Katsuyuki Suga, Michiko Takei, Akito Hara
  • Patent number: 6635110
    Abstract: The invention provides processes for producing a very low dislocation density in heterogeneous epitaxial layers with a wide range of thicknesses, including a thickness compatible with conventional silicon CMOS processing. In a process for reducing dislocation density in a semiconductor material formed as an epitaxial layer upon a dissimilar substrate material, the epitaxial layer and the substrate are heated at a heating temperature that is less than about a characteristic temperature of melting of the epitaxial layer but greater than about a temperature above which the epitaxial layer is characterized by plasticity, for a first time duration. Then the epitaxial layer and the substrate are cooled at a cooling temperature that is lower than the about the heating temperature, for a second time duration. These heating and cooling steps are carried out a selected number of cycles to reduce the dislocation density of the epitaxial layer.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: October 21, 2003
    Assignee: Massachusetts Institute of Technology
    Inventors: Hsin-Chiao Luan, Lionel C. Kimerling
  • Patent number: 6610142
    Abstract: A process for fabricating a semiconductor at a lower crystallization temperature and yet at a shorter period of time, which comprises forming an insulator coating on a substrate; exposing said insulator coating to a plasma; forming an amorphous silicon film on said insulator coating after its exposure to said plasma; and heat treating said silicon film in the temperature range of from 400 to 650° C. or at a temperature not higher than the glass transition temperature of the substrate. The nucleation sites are controlled by selectively exposing the amorphous silicon film to a plasma or by selectively applying a substance containing elements having a catalytic effect thereto. A process for fabricating a thin film transistor using the same is also disclosed.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: August 26, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Hongyong Zhang, Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 6586819
    Abstract: In a sapphire substrate having a heteroepitaxial growth surface, the heteroepitaxial growth surface is parallel to a plane obtained by rotating a (01{overscore (1)}0) plane of the sapphire substrate about a c-axis of the sapphire substrate through 8° to 20° in a crystal lattice of the sapphire substrate. A semiconductor device, electronic component, and crystal growing method are also disclosed.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: July 1, 2003
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventor: Takashi Matsuoka
  • Patent number: 6582512
    Abstract: A method of forming a periodic index of refraction pattern in a superlattice of a solid material to achieve photonic bandgap effects at desired optical wavelengths is disclosed. A plurality of space group symmetries, including a plurality of empty-spaced buried patterns, are formed by drilling holes in the solid material and annealing the solid material to form empty-spaced patterns of various geometries. The empty-spaced patterns may have various sizes and may be formed at different periodicities, so that various photonic band structures can be produced for wavelength regions of interest.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: June 24, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Joseph E. Geusic, Kevin G. Donohoe
  • Patent number: 6569534
    Abstract: An optical material including a crystalline silicon and FexSi2 in the form of dots, islands, or a film is provided. The FexSi2 has a symmetrical monoclinic crystalline structure belonging to the P21/c space group and is synthesized at the surface or in the interior of the crystalline silicon. The monoclinic structure corresponds to a deformed structure of &bgr;-FeSi2 generated by heteroepitaxial stress between the {110} plane of the FexSi2 and the {111} plane of the crystalline silicon. The value of x is 0.85≦x≦1.1. An optical element using the optical material is also provided.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: May 27, 2003
    Assignee: Mitsubishi Materials Corporation
    Inventors: Kenji Yamaguchi, Kazuki Mizushima
  • Patent number: 6458200
    Abstract: A process for fabricating thin film transistors is disclosed, which comprises a two-step laser annealing process as follows: crystallizing the channel portion by irradiating the channel portion with an irradiation beam; and modifying the electric properties of the source and the drain by irradiating the source and the drain with an irradiation beam in a step independent to the first step of crystallizing the channel portion.
    Type: Grant
    Filed: July 12, 1993
    Date of Patent: October 1, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hongyong Zhang
  • Patent number: 6458199
    Abstract: A crystallization apparatus and method that is adapted to crystallize a semiconductor using a non-vacuum process. In the apparatus and method, laser beams are irradiated onto a substrate to grow a crystal unilaterally from the side surface of the substrate. Grain boundaries are minimized under the air atmosphere, so that a crystallization of the substrate can be made in a non-vacuum state to improve the throughput.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: October 1, 2002
    Assignee: LG. Philips LCD Co., Ltd.
    Inventor: Jin Mo Yoon
  • Patent number: 6440211
    Abstract: A laminate article comprises a substrate and a biaxially textured (RE1xRE2(1−x))2O3 buffer layer over the substrate, wherein 0<x<1 and RE1 and RE2 are each selected from the group consisting of Nd, Sm, Eu, Ho, Er, Lu, Gd, Tb, Dy, Tm, and Yb. The (RE1xRE2(1−x))2O3 buffer layer can be deposited using sol-gel or metal-organic decomposition. The laminate article can include a layer of YBCO over the (RE1xRE2(1−x))2O3 buffer layer. A layer of CeO2 between the YBCO layer and the (RE1xRE2(1−x))2O3 buffer can also be include. Further included can be a layer of YSZ between the CeO2 layer and the (RE1xRE2(1−x))2O3 buffer layer. The substrate can be a biaxially textured metal, such as nickel. A method of forming the laminate article is also disclosed.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: August 27, 2002
    Assignee: UT-Battelle, LLC
    Inventors: David B. Beach, Jonathan S. Morrell, Mariappan Paranthaman, Thomas Chirayil, Eliot D. Specht, Amit Goyal
  • Patent number: 6440210
    Abstract: A method for producing self-polarized ferroelectric layers, in particular PZT layers, with a rhombohedral crystal structure includes providing a substrate and heating it to a temperature T1. Afterward the layer with a rhombohedral crystal structure is applied to the substrate by means of a sputtering method. This layer includes a Zr-deficient layer with a Curie temperature TC1 and a Zr-abundant layer with a Curie temperature TC2 wherein TC2<TC1<T1. After the ending of the application process, the heating of the substrate is also discontinued so that the substrate cools. As a result of the cooling the Zr-deficient layer and then the Zr-abundant layer reach their Curie temperature, and change into the ferroelectric phase and become self-polarized in the process. The polarization already present in the Zr-deficient layer induces the polarization in the Zr-abundant layer, with the result that both layers are self-polarized after the cooling process.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: August 27, 2002
    Assignee: Siemens Aktiengesellschaft
    Inventors: Rainer Bruchhaus, Dana Pitzer, Robert Primig, Matthias Schreiter
  • Patent number: 6436186
    Abstract: According to the invention, a complex (M or M′) formed by stacking in a closely contacted state a single crystal &agr;-SiC base material (1) and a polycrystalline plate (2) which is produced into a plate-like shape by the CVD method with interposing an intermediate layer (4 or 4′) containing Si and O as fundamental components, such as silicon rubber between opposing faces of the two members (1) and (2) in a laminated manner is heat-treated at a temperature of 2,200° C. or higher, and under a saturated SiC vapor pressure, thereby causing polycrystal members of the polycrystalline plate (3) to be transformed in a same direction as single crystal of the single crystal &agr;-SiC base material (1) to integrally grow single crystal. Therefore, single crystal SiC of a high quality in which crystal defects and distortion are prevented from occurring and micropipe defects hardly occur can be produced easily and efficiently.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: August 20, 2002
    Assignee: Nissin Electric Co., Ltd.
    Inventors: Kichiya Tanino, Masanobu Hiramoto
  • Patent number: 6358313
    Abstract: A method of manufacturing a crystalline silicon base semiconductor thin film on a substrate, includes the steps of forming a thin film primarily made of silicon on the substrate by forming plasma of a film material gas containing at least a silicon base gas at the vicinity of the substrate; and crystallizing the silicon in the thin film primarily made of the silicon by emitting excited particles produced from an excited particle material gas to the substrate. At least one of the film material gas and the excited particle material gas contains an impurity gas for forming the silicon semiconductor, and thereby the crystalline silicon base semiconductor thin film is formed on the substrate.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: March 19, 2002
    Assignees: Sharp Kabushiki Kaisha, Nissin Electric Co., Ltd.
    Inventors: Shuhei Tsuchimoto, Hirohisa Tanaka, Kiyoshi Ogata, Hiroya Kirimura
  • Patent number: 6350311
    Abstract: A method for growing an epitaxial silicon-germanium layer is described. The method includes removing a native oxide layer on the silicon substrate surface. A HF vapor treatment process is then conducted on the silicon substrate. Thereafter, a germanium layer is formed on the silicon substrate, followed by performing a rapid thermal anneal process under an inert gas to form a silicon-germanium alloy layer on the surface of the silicon substrate.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: February 26, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Feng-Der Chin, Ming-Jang Hwang
  • Patent number: 6350315
    Abstract: Methods for producing doped polycrystalline semiconductors and for producing doped monocrystalline semiconductors from predoped monocrystalline and polycrystalline semiconductors. The methods for producing doped polycrystalline semiconductors may include (1) providing a reactor for chemical vapor deposition, (2) creating a vapor within the reactor that includes a silicon compound and a preselected dopant, and (3) providing a substrate, exposed to the vapor, onto which the silicon and the dopant in the vapor are deposited to form doped polycrystalline silicon. The methods for producing doped monocrystalline semiconductors may include (1) selecting a first amount of a first semiconductor, the first semiconductor having a first concentration of the dopant, (2) selecting a second amount of a second semiconductor, and (3) using the first and second amounts to grow a monocrystalline semiconductor having a preselected concentration of the dopant.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: February 26, 2002
    Assignee: SEH America, Inc.
    Inventor: Douglas G. Anderson
  • Patent number: 6270571
    Abstract: A method for producing narrow wires including titanium oxide of high crystallinity and diameter of the order of nanometer, in particular whiskers of titanium oxide, and including a first step of preparing a base having a titanium-including surface, second step of discretely depositing a material other than titanium over the above surface, and third step of thermally treating the above surface, obtained by the second step, in a titanium-oxidizing atmosphere.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: August 7, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsuya Iwasaki, Tohru Den