Epitaxy Formation Patents (Class 117/9)
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Patent number: 6217842Abstract: According to the present invention, a complex (M) which is formed by growing a polycrystalline &bgr;-SiC plate 2 having a thickness of 10 &mgr;m or more on the surface of a single crystal &agr;-SiC base material 1 by the PVD method or the thermal CVD method is heat-treated at a temperature of the range of 1,650 to 2,400° C., whereby polycrystals of the polycrystalline cubic &bgr;-SiC plate 2 are transformed into a single crystal, and the single crystal oriented in the same direction as the crystal axis of the single crystal &agr;-SiC base material 1 is grown. As a result, single crystal SiC of high quality which is substantially free from micropipe defects and defects affected by the micropipe defects can be produced easily and efficiently.Type: GrantFiled: February 3, 1999Date of Patent: April 17, 2001Assignee: Nippon Pillar Packing Co., Ltd.Inventor: Kichiya Tanino
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Patent number: 6217647Abstract: To produce monocrystalline layers of conducting or semiconducting materials on porous monocrystalline layers of the same material in a reproducible and time-saving manner, a method is provided which involves applying an amorphous layer of the same material to the porous material and converting the amorphous layer to a monocrystalline layer by tempering.Type: GrantFiled: January 21, 1999Date of Patent: April 17, 2001Assignee: Robert Bosch GmbHInventors: Franz Laermer, Wilhelm Frey
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Patent number: 6217650Abstract: In an epitaxial-wafer fabricating process for epitaxially growing a silicon layer on the surface of a silicon wafer having the crystal orientation <100> or <111> and an inclination angle of 0°±1° in a reactive gas at a atmosphereicpressure, a growth temperature T is lower than a normal growth temperature by 50° C. to 100° C. during the process of epitaxial growth.Type: GrantFiled: June 15, 1999Date of Patent: April 17, 2001Assignee: Komatsu Electronic Metals Co., Ltd.Inventors: Takeshi Hirose, Hiroyuki Kawahara, Takeo Tamura, Masayoshi Danbata
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Patent number: 6204156Abstract: A process to fabricate a thin film transistor using an intrinsic polycrystalline silicon film, by a method of: preparing a semiconductor assembly; forming an insulation layer on a substrate; forming a first amorphous silicon layer on said insulation layer; forming silicon nucleation sites on said first amorphous silicon layer; converting said first amorphous silicon layer into hemispherical grained silicon, said hemispherical grained silicon being formed about said silicon nucleation sites; forming a second amorphous silicon layer covering said hemispherical grained silicon; annealing said second amorphous silicon layer to convert said second amorphous silicon layer into a grained silicon film, said grained silicon film being formed about said hemispherical grained silicon and having a dimension of approximately 0.1 microns to 0.Type: GrantFiled: September 2, 1999Date of Patent: March 20, 2001Assignee: Micron Technology, Inc.Inventor: Er-Xuan Ping
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Patent number: 6203772Abstract: The single crystal SiC according to the present invention is produced in the following manner. Two complexes M in each of which a polycrystalline film 2 of &bgr;-SiC (or &agr;-SiC) is grown on the surface of a single crystal &agr;-SiC substrate 1 by thermochemical deposition, and the surface 2a of the polycrystalline film 2 is ground so that the smoothness has a surface roughness of 200 angstroms RMS or smaller, preferably 100 to 50 angstroms RMS are subjected to a heat treatment under a state where the complexes are closely fixed to each other via their ground surfaces 2a′, at a temperature of 2,000° C. or higher and in an atmosphere of a saturated SiC vapor pressure, whereby the polycrystalline films 2 of the complexes M are recrystallized to grow a single crystal which is integrated with the single crystal &agr;-SiC substrates 1. Large-size single crystal SiC in which impurities, micropipe defects, and the like do not remain, and which has high quality can be produced with high productivity.Type: GrantFiled: November 6, 1998Date of Patent: March 20, 2001Assignee: Nippon Pillar Packing Co., Ltd.Inventors: Kichiya Tanino, Masanobu Hiramoto
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Patent number: 6198530Abstract: A method for forming an optical device includes the steps of providing a first plate having a first face defining a recess, filling the recess with a material which can be crystallized, and covering the first face and the recess with a second plate having a second face, so that the second face is in contact with the first face and the material in the recess is completely enclosed by the first and second plates. The material in the recess is thereby protected from chemical and mechanical damage, as well as evaporation. In addition, the plates can be transparent, allowing the material in the recess to be visually monitored. A grown crystalline film packed in the cell can be used as a non-liner and/or electro-optical device.Type: GrantFiled: March 2, 1998Date of Patent: March 6, 2001Assignee: University of Puerto RicoInventor: Alexander Leyderman
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Patent number: 6187279Abstract: In single crystal SiC according to the present invention, a single crystal &agr;-SiC substrate and a polycrystalline &bgr;-SiC plate are laminated to each other for fixation, the single crystal &agr;-Sic substrate and the polycrystalline &bgr;-SiC plate are subjected to heat treatment under an inert gas atmosphere and a saturated SiC vapor atmosphere, whereby the single crystallization owing to solid-phase transformation of the polycrystalline &bgr;-SiC plate and a progress of the single crystallization to a surface direction wherein a contact point is regarded as a starting point make a whole surface of layer of the polycrystalline &bgr;-SiC plate grow efficiently into a single crystal integrated with the single crystal &agr;-SiC substrate, whereby it is possible to produce single crystal SiC having high quality with high productivity, which is substantially free from lattice defects and micropipe defects.Type: GrantFiled: March 31, 1999Date of Patent: February 13, 2001Assignee: Nippon Pillar Packing Co., Ltd.Inventors: Kichiya Tanino, Masanobu Hiramoto
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Patent number: 6176922Abstract: A method is presented for crystallizing a thin film on a substrate by generating a beam of pulsed optical energy, countouring the intensity profile of the beam, and illuminating the thin film with the beam to crystallize the thin film into a single crystal lattice structure.Type: GrantFiled: October 6, 1999Date of Patent: January 23, 2001Assignee: The United States of America as represented by the Secretary of the NavyInventors: Monti E. Aklufi, Stephen D. Russell
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Patent number: 6171389Abstract: Methods for producing doped polycrystalline semiconductors and for producing doped monocrystalline semiconductors from predoped monocrystalline and polycrystalline semiconductors. The methods for producing doped polycrystalline semiconductors may include (1) providing a reactor for chemical vapor deposition, (2) creating a vapor within the reactor that includes a silicon compound and a preselected dopant, and (3) providing a substrate, exposed to the vapor, onto which the silicon and the dopant in the vapor are deposited to form doped polycrystalline silicon. The methods for producing doped monocrystalline semiconductors may include (1) selecting a first amount of a first semiconductor, the first semiconductor having a first concentration of the dopant, (2) selecting a second amount of a second semiconductor, and (3) using the first and second amounts to grow a monocrystalline semiconductor having a preselected concentration of the dopant.Type: GrantFiled: September 30, 1998Date of Patent: January 9, 2001Assignee: SEH America, Inc.Inventor: Douglas G. Anderson
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Patent number: 6153165Abstract: According to the present invention, a complex (M) which is formed by growing a polycrystalline .beta.-SiC plate 2 on the surface of a single crystal .alpha.-SiC base material 1 by the thermal CVD method is heat-treated at a high temperature of 1,900 to 2,400.degree. C., whereby polycrystals of the polycrystalline cubic .beta.-SiC plate are transformed into a single crystal, so that the single crystal is oriented in the same direction as the crystal axis of the single crystal .alpha.-SiC base material and integrated with the single crystal of the single crystal .alpha.-SiC base material to be largely grown. As a result, single crystal SiC of high quality which has a very reduced number of lattice defects and micropipe defects can be efficiently produced while ensuring a sufficient size in terms of area.Type: GrantFiled: December 29, 1998Date of Patent: November 28, 2000Assignee: Nippon Pillar Packing Co., Ltd.Inventor: Kichiya Tanino
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Patent number: 6153166Abstract: According to the present invention, a complex (M) which is formed by stacking a polycrystalline .beta.-SiC plate 2 on the surface of a single crystal .alpha.-SiC base material 1 in a close contact state via a polished face or grown in a layer-like manner by the thermal CVD method is heat-treated in a temperature range of 1,850 to 2,400.degree. C., whereby polycrystals of the polycrystalline cubic .beta.-Sic plate are transformed into a single crystal, and the single crystal oriented in the same direction as the crystal axis of the single crystal .alpha.-SiC base material is grown. As a result, large single crystal SiC of high quality which is free from micropipe defects, lattice defects, generation of grain boundaries due to intrusion of impurities, and the like can be produced easily and efficiently.Type: GrantFiled: February 3, 1999Date of Patent: November 28, 2000Assignee: Nippon Pillar Packing Co., Ltd.Inventor: Kichiya Tanino
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Patent number: 6143267Abstract: A complex (M) which is formed by growing a polycrystalline .beta.-SiC plate 4 by the thermal CVD method on crystal orientation faces which are unified in one direction of plural plate-like single crystal .alpha.-SiC pieces 2 that are stacked and closely contacted is subjected to a heat treatment at a temperature in the range of 1,850 to 2,400.degree. C., whereby a single crystal which is oriented in the same direction as the crystal axes of the single crystal .alpha.-SiC pieces 2 is grown from the crystal orientation faces of the single crystal .alpha.-SiC pieces toward the polycrystalline .beta.-SiC plate 4. As a result, single crystal SiC of a high quality in which crystalline nuclei, impurities, micropipe defects, and the like are not substantially generated in an interface can be produced easily and efficiently.Type: GrantFiled: April 23, 1999Date of Patent: November 7, 2000Assignee: Nippon Pillar Packing Co., Ltd.Inventor: Kichiya Tanino
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Patent number: 6143659Abstract: A method for forming an Al layer using an atomic layer deposition method is disclosed. First, a semiconductor substrate is loaded into a deposition chamber. Then, an Al source gas is supplied into the deposition chamber and the Al source gas is chemisorbed into the semiconductor substrate to form the Al layer. Next, a purge gas is supplied onto the deposition chamber without supplying the Al source gas so that the unreacted Al source gas is removed, thereby completing the Al layer. To form an Al layer to a required thickness, the step of supplying the Al source gas and the step of supplying the purge gas are repeatedly performed, thereby forming an Al atomic multilayer. Therefore, the uniformity and step coverage of the Al layer can be greatly improved.Type: GrantFiled: August 27, 1998Date of Patent: November 7, 2000Assignee: Samsung Electronics, Co., Ltd.Inventor: Hyeun-seog Leem
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Patent number: 6126741Abstract: A polycrystalline carbon body is converted to a different crystallography by directing an infrared laser beam at a crystal boundary interface. By using a beam having a 5.3 micron wavelength so as to fall within a 5-9 micron range of normal spectral transmittance of the carbon, the interface is heated for solid state conversion by passing the beam through a forward portion of the body without appreciably heating the forward portion. During heating, the interface propagates through the body, thus converting an ever-decreasing aft portion of the body to the different crystallography.Type: GrantFiled: December 7, 1998Date of Patent: October 3, 2000Assignee: General Electric CompanyInventors: Marshall Gordon Jones, Hsin-Pang Wang
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Solution synthesis of mixed-metal chalcogenide nanoparticles and spray deposition of precursor films
Patent number: 6126740Abstract: A colloidal suspension comprising metal chalcogenide nanoparticles and a volatile capping agent. The colloidal suspension is made by reacting a metal salt with a chalcogenide salt in an organic solvent to precipitate a metal chalcogenide, recovering the metal chalcogenide, and admixing the metal chalcogenide with a volatile capping agent. The colloidal suspension is spray deposited onto a substrate to produce a semiconductor precursor film which is substantially free of impurities.Type: GrantFiled: January 27, 1998Date of Patent: October 3, 2000Assignee: Midwest Research InstituteInventors: Douglas L. Schulz, Calvin J. Curtis, David S. Ginley -
Patent number: 6106734Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diaphragm which is made of a single-crystalline material can be easily manufactured through no junction.Type: GrantFiled: August 25, 1997Date of Patent: August 22, 2000Assignees: Mega Chips Corporation, Crystal Device CorporationInventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
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Patent number: 6099639Abstract: A method for solid state formation of diamond includes providing a diamond growth substrate, such as single-crystal silicon, forming on the diamond growth substrate an alloy of carbon and a metal which permits carbon to exist in a matrix therein, and causing carbon atoms from the alloy to precipitate on the diamond growth substrate in a diamond cubic lattice. The alloy may be an alloy of aluminum and carbon. The alloy is annealed in a hydrogen ambient to cause diffusion of hydrogen through the alloy to the surface of the substrate, providing a high concentration of hydrogen at the interface between the substrate and the alloy. The alloy is heated to cause carbon atoms in the alloy to diffuse through the alloy to the interface and form diamond.Type: GrantFiled: November 17, 1992Date of Patent: August 8, 2000Assignee: National Semiconductor CorporationInventor: Michael E. Thomas
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Patent number: 6096127Abstract: The present invention is directed to a method for forming dielectric thin films having substantially reduced electrical losses at microwave and millimeter wave frequencies relative to conventional dielectric thin films. The reduction in losses is realized by dramatically increasing the grain sizes of the dielectric films, thereby minimizing intergranular scattering of the microwave signal due to grain boundaries and point defects. The increase in grain size is realized by heating the film to a temperature at which the grains experience regrowth. The grain size of the films can be further increased by first depositing the films with an excess of one of the compoents, such that a highly mobile grain boundary phase is formed.Type: GrantFiled: February 28, 1997Date of Patent: August 1, 2000Assignee: Superconducting Core Technologies, Inc.Inventors: Duane Brian Dimos, Robert William Schwartz, Mark Victor Raymond, Husam Niman Al-Shareef, Carl Mueller, David Galt
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Patent number: 6093243Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.Type: GrantFiled: October 28, 1997Date of Patent: July 25, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
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Patent number: 6077344Abstract: A method is disclosed for forming a biaxially textured buffer layer on a biaxially oriented metal substrate by using a sol-gel coating technique followed by pyrolyzing/annealing in a reducing atmosphere. This method is advantageous for providing substrates for depositing electronically active materials thereon.Type: GrantFiled: September 2, 1997Date of Patent: June 20, 2000Assignee: Lockheed Martin Energy Research CorporationInventors: Shara S. Shoup, Mariappan Paranthamam, David B. Beach, Donald M. Kroeger, Amit Goyal
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Patent number: 6053973Abstract: The surface 1a of a single crystal .alpha.-SiC substrate 1 is adjusted so as to have a surface roughness equal to or lower than 2,000 angstroms RMS, and preferably equal to or lower than 1,000 angstroms RMS. On the surface 1a of the single crystal .alpha.-SiC substrate 1, a polycrystalline .alpha.-SiC film 2 is grown by thermal CVD to form a complex is placed in a porous carbon container and the carbon container is covered with .alpha.-SiC powder. The complex is subjected to a heat treatment at a temperature equal to or higher than a film growing temperature, i.e., in the range of 1,900 to 2,400.degree. C. in an argon gas flow, whereby single crystal .alpha.-SiC is integrally grown on the single crystal .alpha.-SiC substrate 1 by crystal growth and recrystallization of the polycrystalline .alpha.-SiC film 2. It is possible to stably and efficiently produce single crystal SiC of a large size which has a high quality and in which any crystal nucleus is not generated.Type: GrantFiled: November 6, 1998Date of Patent: April 25, 2000Assignee: Nippon Pillar Packing Co., Ltd.Inventors: Kichiya Tanino, Masanobu Hiramoto
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Patent number: 6024792Abstract: In the method for manufacturing monocrystalline structures, parts or workpieces of metallic super-alloys on substrates with a monocrystalline structure or monocrystalline structures, the surface of the substrate is melted with an energy beam of high energy density from an energy source. The material which is to be introduced into the monocrystalline structure is supplied to the melted region of the substrate. The supplied material is completely melted. The energy input with the energy beam is regulated and/or controlled in such a manner that the speed of solidification and the temperature gradient lie in the dendritic crystalline region in the GV diagram, outside the globulitic region.Type: GrantFiled: February 20, 1998Date of Patent: February 15, 2000Assignee: Sulzer Innotec AGInventors: Wilfried Kurz, Werner Gaumann, Hans-Werner Bieler, Jean-Daniel Wagniere, Hansjakob Rusterholz
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Patent number: 5997634Abstract: A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO.sub.2 and Si.sub.3 N.sub.4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material.Type: GrantFiled: November 14, 1996Date of Patent: December 7, 1999Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Sujit Sharan
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Patent number: 5993538Abstract: In order to form a single-crystalline thin film on a polycrystalline substrate using plasma CVD, a downwardly directed mainly neutral Ne atom current is formed by an ECR ion generator (2). A reaction gas such as silane gas which is supplied from a reaction gas inlet pipe (13) is sprayed onto an SiO.sub.2 substrate (11) by an action of the Ne atom current, so that an amorphous Si thin film is grown on the substrate (11) by a plasma CVD reaction. At the same time, a part of the Ne atom current having high directivity is directly incident upon the substrate (11), while another part thereof is incident upon the substrate (11) after its course is bent by a reflector (12). The reflector (12) is so set that all directions of the parts of the Ne atom current which are incident upon the substrate (11) are perpendicular to densest planes of single-crystalline Si.Type: GrantFiled: February 13, 1996Date of Patent: November 30, 1999Assignee: Mega Chips CorporationInventors: Toshifumi Asakawa, Masahiro Shindo, Toshikazu Yoshimizu, Sumiyoshi Ueyama
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Patent number: 5922125Abstract: In order to obtain a thin-film transistor having high characteristics using a metal element for accelerating the crystallization of silicon, a nickel element is selectively added to the surface of an amorphous silicon film (103) in regions (101) and (102) and regions (108) to (110), and a heat treatment is carried out to grow crystals (horizontal growth) in directions parallel to the substrate as indicated by arrows (104) to (107). At this point, the regions (108) to (110) having a width of 5 .mu.m or less serve as stopper regions so that horizontal growth starting from the regions (101) and (102) stops there. In this way, the horizontal growth regions can be formed with high controllability. Then a circuit such as a shift register can be constructed with a region having the same crystal growth form.Type: GrantFiled: December 10, 1996Date of Patent: July 13, 1999Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hongyong Zhang
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Patent number: 5893741Abstract: A method for formation of both local innerconnection and silicidation of source/drain transistors using the deposition of a blanket silicon layer over the entire top surface of the transistors and selectively stripping of unwanted portions of the silicon layer is disclosed. The method includes the step of applying a photoresist mask to map out where the local interconnection and source/drain are to be located. The final recited step is to deposit a thin metal layer to provide for the silicidation to complete the transistor. The silicon layer that is deposited has a thickness of 20 to 300 millimeters, and the thin metal layer is either cobalt or titanium having a thickness of 10 millimeters to 100 millimeters.Type: GrantFiled: February 7, 1997Date of Patent: April 13, 1999Assignee: National Science CouncilInventor: Tiao-yuan Huang
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Patent number: 5891244Abstract: The present invention provides a process for preparing SOI wafer, more specifically, a process for preparing a large-sized SOI wafer of high quality of crystallization employing an apparatus for the manufacture of the SOI wafer in a simple and efficient manner. The apparatus for the manufacture of SOI wafer of the invention comprises electric furnace for heating polycrystalline silicon filled in a heat-resistant container; means for moving up and down of an insulating substrate whose one side is accompanied with silicon single crystalline seed, and immersing the substrate in the molten silicon filled in the heat-resistant container to form a thin single crystalline film on the substrate; and, shapers to keep a constant thickness of the thin single crystalline film which is formed on the insulating substrate by the moving means.Type: GrantFiled: August 27, 1996Date of Patent: April 6, 1999Assignee: Korea Advanced Institute of Science and TechnologyInventors: Do-Hyun Kim, Jong-Hoe Wang
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Patent number: 5879447Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.Type: GrantFiled: June 7, 1995Date of Patent: March 9, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
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Patent number: 5843225Abstract: A process for fabricating a semiconductor at a lower crystallization temperature and yet at a shorter period of time, which comprises forming an insulator coating on a substrate; exposing said insulator coating to a plasma; forming an amorphous silicon film on said insulator coating after its exposure to said plasma; and heat treating said silicon film in the temperature range of from 400.degree. to 650.degree. C. or at a temperature not higher than the glass transition temperature of the substrate. The nucleation sites are controlled by selectively exposing the amorphous silicon film to a plasma or by selectively applying a substance containing elements having a catalytic effect thereto. A process for fabricating a thin film transistor using the same is also disclosed.Type: GrantFiled: June 7, 1995Date of Patent: December 1, 1998Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Takayama, Yasuhiko Takemura, Hongyong Zhang, Shunpei Yamazaki
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Patent number: 5837053Abstract: A single crystal material is prepared by forming a layer of an amorphous substance over a surface of a substrate of a single crystal having the same chemical composition as that of the amorphous substance, the resulting composite material is heated to epitaxially grow the amorphous layer into a single crystal layer. A composite material for producing such a single crystal material is also disclosed which includes a substrate of a single crystal, and a layer of an amorphous substance having the same chemical composition as that of the substrate, the layer having such a thickness that the layer as a whole can epitaxially grow to make a single crystal layer.Type: GrantFiled: November 28, 1995Date of Patent: November 17, 1998Assignee: International Superconductivity Technology CenterInventors: Furen Wang, Tadataka Morishita
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Patent number: 5803965Abstract: A method and system for manufacturing a semiconductor device having a semiconductor layer using a pulsed laser includes the steps of generating a laser beam using a solid laser source, generating a multi-harmonic wave from the laser beam using a multi-harmonic oscillator, filtering the multi-harmonic wave, and irradiating the filtered wave onto the semiconductor layer.Type: GrantFiled: August 13, 1996Date of Patent: September 8, 1998Assignee: LG Electronics, Inc.Inventor: Jung Kee Yoon
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Patent number: 5759879Abstract: A method for forming a polycrystalline silicon film includes the steps of: forming at least one step on a surface of an insulating substrate; depositing a first amorphous silicon film on the substrate; annealing the first amorphous silicon film so as to change the first amorphous silicon film into a first polycrystalline silicon film; patterning the first polycrystalline silicon film to form a patterned film at the at least one step of the insulating substrate, the patterned film having at least one side face; depositing a second amorphous silicon film on the insulating substrate so as to cover the patterned film; and annealing the second amorphous silicon film so as to change the second amorphous silicon film into a second polycrystalline silicon film by using the at least one side face of the pattered film as a seed crystal for lateral solid-phase crystallization.Type: GrantFiled: March 6, 1996Date of Patent: June 2, 1998Assignee: Sharp Kabushiki KaishaInventor: Yasunori Iwasaki
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Patent number: 5753555Abstract: A method is provided for forming an epitaxial silicon layer on a diffused region of a silicon substrate having an anisotropic ratio of more than 3:1 between the growth rate in the direction perpendicular to the substrate surface and the growth rate in the direction parallel to the substrate surface. The epitaxial silicon layer serves as a contact plug which does not contact an adjacent contact plug formed by the same process in order to obtain a reliable semiconductor memory device with a high throughput, which is free from short circuit failure.Type: GrantFiled: October 24, 1996Date of Patent: May 19, 1998Assignee: NEC CorporationInventor: Hiromitsu Hada
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Patent number: 5746823Abstract: A method for forming an optical device includes the steps of providing a first plate having a first face defining a recess, filling the recess with a material which can be crystallized, and covering the first face and the recess with a second plate having a second face, so that the second face is in contact with the first face and the material in the recess is completely enclosed by the first and second plates. The material in the recess is thereby protected from chemical and mechanical damage, as well as evaporation. In addition, the plates can be transparent, allowing the material in the recess to be visually monitored. A grown crystalline film packed in the cell can be used as a non-liner and/or electro-optical device.Type: GrantFiled: September 8, 1995Date of Patent: May 5, 1998Assignee: University of Puerto RicoInventor: Alexander Leyderman
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Patent number: 5735949Abstract: A buried amorphous layer on a crystalline substrate with a monocrystalline surface layer, which is transformed into a mixed-crystal or chemical compound, avoids the formation of lattice defects at the interface even where the lattice parameters of the substrate and the monocrystalline layer are not matched.Type: GrantFiled: September 13, 1991Date of Patent: April 7, 1998Assignee: Forschungszentrum Julich GmbHInventors: Siegfried Mantl, Bernd Hollander, Rainer Butz
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Patent number: 5711803Abstract: A process for the preparation of a semiconductor film. The process comprises depositing nanoparticles of a semiconductor material onto a substrate whose surface temperature during nanoparticle deposition thereon is sufficient to cause substantially simultaneous fusion of the nanoparticles to thereby coalesce with each other and effectuate film growth.Type: GrantFiled: September 29, 1995Date of Patent: January 27, 1998Assignee: Midwest Research InstituteInventors: Martin Pehnt, Douglas L. Schulz, Calvin J. Curtis, David S. Ginley
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Patent number: 5711804Abstract: Oxide coatings are formed with a desired crystallographic texture over a large surface area. A metallic substrate is electrodeposited or vacuum deposited with a preferred crystallographic orientation, and a sol-gel/thermal process is used to form a "pseudo-epitaxial" oxide coating having crystallites that are influenced by the crystallographic orientation of the substrate. In one embodiment, p-type nickel oxide coatings with desirable electronic properties are produced by sol-gel/thermal processing on nickel substrates electrodeposited from a sulfamate nickel bath at a relatively high current density and low temperature. The electrodeposited nickel substrate has a strong Ni{100} preferred orientation. Epitaxial effects during sol-gel/thermal formation of NiO on the electrodeposited substrate enhance the extent to which the NiO{100} and NiO{111} crystal facets are aligned parallel to the coating surface, and minimize the NiO{110} orientation.Type: GrantFiled: May 3, 1996Date of Patent: January 27, 1998Assignee: Rockwell International CorporationInventors: D. Morgan Tench, Leslie F. Warren, Jr., Young J. Chung
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Patent number: 5676752Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is optionally separated so that the substrate can be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.Type: GrantFiled: August 16, 1994Date of Patent: October 14, 1997Assignee: Massachusetts Institute of TechnologyInventors: Carl O. Bozler, John C. C. Fan, Robert W. McClelland
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Patent number: 5611854Abstract: A method of fabricating bulk superconducting material including RBa.sub.2 Cu.sub.3 O.sub.7-.delta. comprising heating compressed powder oxides and/or carbonates of R and Ba and Cu present in mole ratios to form RBa.sub.2 Cu.sub.3 O.sub.7-.delta. in physical contact with an oxide single crystal seed to a temperature sufficient to form a liquid phase in the RBa.sub.2 Cu.sub.3 O.sub.7-.delta. while maintaining the single crystal seed solid to grow the superconducting material and thereafter cooling to provide a material including RBa.sub.2 Cu.sub.3 O.sub.7-.delta.. R is a rare earth or Y or La and the single crystal seed has a lattice mismatch with RBa.sub.2 Cu.sub.3 O.sub.7-.delta. of less than about 2% at the growth temperature. The starting material may be such that the final product contains a minor amount of R.sub.2 BaCuO.sub.5.Type: GrantFiled: September 21, 1995Date of Patent: March 18, 1997Assignee: The University of ChicagoInventors: Boyd W. Veal, Arvydas Paulikas, Uthamalingam Balachandran, Wei Zhong
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Patent number: 5549747Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is optionally separated so that the substrate can be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.Type: GrantFiled: April 14, 1994Date of Patent: August 27, 1996Assignee: Massachusetts Institute of TechnologyInventors: Carl O. Bozler, John C. C. Fan, Robert W. McClelland
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Patent number: 5463975Abstract: A process for producing a crystal comprises the step of applying crystal forming treatment on a light-transmissive substrate having a non-nucleation surface (S.sub.NDS) of a small nucleation density and a nucleation surface (S.sub.NDL) of a nucleation density (ND.sub.L) greater than the nucleation density (N.sub.DS) of said non-nucleation surface (S.sub.NDS) and formed of an amorphous material (M.sub.L) different from the material (M.sub.S) forming the non-nucleation surface (S.sub.NDS) at a small area sufficient to effect crystal growth from only a single nucleus to form a single crystal nucleus on the nucleation surface (S.sub.NDL), thereby growing a single crystal from the single nucleus, and the step of reducing the crystal defects of the crystal in the vicinity of the interface with the substrate by irradiation of light from the side of the substrate.Type: GrantFiled: July 12, 1993Date of Patent: November 7, 1995Assignee: Canon Kabushiki KaishaInventor: Takao Yonehara
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Patent number: 5447117Abstract: A crystal article comprises a substrate having an insulating amorphous surface and monocrystal formed on the substrate. The monocrystal is formed by providing a primary seed in the form of a film with an area 100 .mu.m.sup.2 or less arranged in a desired pattern on the surface of the substrate acting as a non-nucleation surface with a small nucleation density, then subjecting the primary seed to thermal treatment to convert it to a monocrystalline seed, and subsequently subjecting the monocrystalline seed to crystal growth treatment to allow a monocrystal to grow beyond the monocrystalline seed and cover the non-nucleation surface.Type: GrantFiled: October 24, 1994Date of Patent: September 5, 1995Assignee: Canon Kabushiki KaishaInventors: Takao Yonehara, Kenji Yamagata, Yuji Nishigaki
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Patent number: 5445107Abstract: A silicon-on insulator film (38) is formed by solid phase epitaxial re-growth. A layer of amorphous silicon (36) is formed such that it is only in direct contact with an underlying portion of a silicon substrate (12). The layer of amorphous silicon (36) is subsequently annealed to form a monocrystalline layer of epitaxial silicon (38). Because the amorphous silicon layer (36) is in contact with only the silicon substrate (12), during the re-growth process, the resulting epitaxial layer (38) is formed with a reduced number of crystal defects. The resulting epitaxial silicon layer (38) may then be used to form semiconductor devices.Type: GrantFiled: November 22, 1993Date of Patent: August 29, 1995Assignee: Motorola, Inc.Inventors: Scott S. Roth, Howard C. Kirsch
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Patent number: 5443030Abstract: A lower capacitor electrode is formed on the basic plate 1, and thereafter a ferroelectric film, for example, a PZT film having the Pb is formed. ITO, RuO2, SnO2 which are Pt or oxide conductive material are formed as a cap layer into 200 .ANG. or more in film thickness by a sputtering method or silicone oxide film or the like are formed with 200A or more in film thickness by a thermal CVD method. Thereafter, a thermal operating operation is effected. By the prevention of the Pb from being evaporated at the thermal processing time, the elaborate ferroelectric film of stoichiometrical perovskite construction can be formed.Type: GrantFiled: October 11, 1994Date of Patent: August 22, 1995Assignee: Sharp Kabushiki KaishaInventors: Kazuya Ishihara, Shigeo Onishi, Masaya Komai
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Patent number: 5398639Abstract: Films of hexagonal boron nitride are converted to a highly desirable cubic-like phase of boron nitride. The transformation is achieved by annealing the hBN material at temperatures below 1000.degree. C. The conversion may be conducted in a hydrogen, nitrogen, ammonia, vacuum, or inert gas containing atmosphere.Type: GrantFiled: November 12, 1993Date of Patent: March 21, 1995Assignee: General Motors CorporationInventors: Gary L. Doll, Joseph P. Heremans
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Patent number: 5373803Abstract: A method of epitaxially growing semiconductor crystal by which a single crystal region which is superior in quality can be selectively formed at a high throughput without employing the lithography technique. A shield mask is formed on an upper face of an amorphous semiconductor layer formed on substrate, and excimer laser light is irradiated upon the amorphous semiconductor layer using the shield mask to produce, in the amorphous semiconductor layer, a core from which crystal is to be grown. After the shield mask is removed, low temperature solid phase annealing processing for the amorphous semiconductor layer is performed to grow crystal from the core to form a single crystal region in the amorphous semiconductor layer. Alternatively, the silicon core is formed by irradiating an energy beam, which is capable of being converged into a thin beam and being used to directly draw a picture, at a predetermined position of the amorphous silicon film.Type: GrantFiled: September 30, 1992Date of Patent: December 20, 1994Assignee: Sony CorporationInventors: Takashi Noguchi, Toshiharu Suzuki
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Patent number: 5357899Abstract: The subject invention provides a silicon membrane material made from silicon that is epitaxially deposited at low temperatures greater than or equal to 500.degree. C. and doped with controlled amounts of boron and germanium. A silicon membrane structure is provided and made by one or more layers of ultra thin epitaxially deposited silicon layers that are precisely controlled in both thickness and composition. At least one of the layers is doped with boron in a concentration range greater than 2.times.10.sup.20 atoms of boron per cubic centimeter of silicon, or with germanium in a concentration range greater than 5.times.10.sup.20 atoms of germanium per cubic centimeter of silicon, or with a combination of boron and germanium in these concentration ranges. A silicon membrane fabrication process is also provided which requires no additional masking film to protect the membrane surface during KOH etching of the bulk silicon substrate.Type: GrantFiled: September 13, 1993Date of Patent: October 25, 1994Assignee: International Business Machines CorporationInventors: Ernest Bassous, Bernard S. Meyerson, Kevin J. Uram